AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 801

KIT EVAL FOR AT91SAM9G45

AT91SAM9G45-EKES

Manufacturer Part Number
AT91SAM9G45-EKES
Description
KIT EVAL FOR AT91SAM9G45
Manufacturer
Atmel
Series
AT91SAM Smart ARMr
Type
MCUr

Specifications of AT91SAM9G45-EKES

Contents
Board
Processor To Be Evaluated
SAM9G45
Data Bus Width
32 bit
Interface Type
I2C, SPI, UART
Maximum Operating Temperature
+ 50 C
Minimum Operating Temperature
- 10 C
Operating Supply Voltage
1.8 V to 3.3 V
For Use With/related Products
AT91SAM9G45
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
Q4626953
36.13.8
Name:
Addresses:
Access:
• CSTOCYC: Completion Signal Timeout Cycle Number
• CSTOMUL: Completion Signal Timeout Multiplier
These fields determine the maximum number of Master Clock cycles that the HSMCI waits between two data block trans-
fers. Its value is calculated by (CSTOCYC x Multiplier).
These fields determine the maximum number of Master Clock cycles that the HSMCI waits between the end of the data
transfer and the assertion of the completion signal. The data transfer comprises data phase and the optional busy phase. If
a non-DATA ATA command is issued, the HSMCI starts waiting immediately after the end of the response until the comple-
tion signal.
Multiplier is defined by CSTOMUL as shown in the following table:
If the data time-out set by CSTOCYC and CSTOMUL has been exceeded, the Completion Signal Time-out Error flag
(CSTOE) in the HSMCI Status Register (HSMCI_SR) raises.
6438F–ATARM–21-Jun-10
31
23
15
7
HSMCI Completion Signal Timeout Register
0
0
0
0
1
1
1
1
30
22
14
HSMCI_CSTOR
0xFFF8001C (0), 0xFFFD001C (1)
Read-write
6
CSTOMUL
29
21
13
5
CSTOMUL
0
0
1
1
0
0
1
1
28
20
12
4
27
19
11
3
0
1
0
1
0
1
0
1
26
18
10
2
CSTOCYC
Multiplier
AT91SAM9G45
25
17
9
1
1048576
65536
1024
4096
128
256
16
1
24
16
8
0
801

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