AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 301
![KIT EVAL FOR AT91SAM9G45](/photos/9/26/92642/at91sam9g45-ekes_sml.jpg)
AT91SAM9G45-EKES
Manufacturer Part Number
AT91SAM9G45-EKES
Description
KIT EVAL FOR AT91SAM9G45
Manufacturer
Atmel
Series
AT91SAM Smart ARMr
Type
MCUr
Datasheets
1.AT91SAM9G45-EKES.pdf
(56 pages)
2.AT91SAM9G45-EKES.pdf
(1218 pages)
3.AT91SAM9G45-EKES.pdf
(66 pages)
Specifications of AT91SAM9G45-EKES
Contents
Board
Processor To Be Evaluated
SAM9G45
Data Bus Width
32 bit
Interface Type
I2C, SPI, UART
Maximum Operating Temperature
+ 50 C
Minimum Operating Temperature
- 10 C
Operating Supply Voltage
1.8 V to 3.3 V
For Use With/related Products
AT91SAM9G45
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
Q4626953
- Current page: 301 of 1218
- Download datasheet (19Mb)
25.2.1
25.2.1.1
25.2.1.2
6438F–ATARM–21-Jun-10
Main Application Modes
Normal Mode
USB HS and LP-DDR Mode
Figure 25-1. AT91SAM9G45 Power Management Controller Block Diagram
The Power Management Controller provides 3 main application modes.
• PLLA and UPLL are running respectively at 400 MHz and 480 MHz
• USB Device High Speed and Host EHCI High Speed operations are allowed
• Full Speed OHCI input clock is UPLLCK, USBDIV is 9 (division by 10)
• System Input clock is PLLACK, PCK is 400 MHz
• MDIV is ‘11’, MCK is 133 MHz
• DDR2 can be used at up to 133 MHz
• Only UPLL is running at 480 MHz, PLLA power consumption is saved
• USB Device High Speed and Host EHCI High Speed operations are allowed
• Full Speed OHCI input clock is UPLLCK, USBDIV is 9 (division by 10)
• System Input clock is UPLLCK, Prescaler is 2, PCK is 240 MHz
• MDIV is ‘01’, MCK is 120 MHz
• Only LP-DDR can be used at up to 120 MHz
PLLACK
/1,/2
UPLLCK
MAINCK
SLCK
USBS
Master Clock Controller
/1,/2,/4,.../64
Prescaler
UPLLCK
MAINCK
USBDIV+1
SLCK
Programmable Clock Controller
/1 /2
X /1 /1.5 /2
/4
Divider
/1,/2,/4,...,/64
/3 /4
Prescaler
UHP48M
UHP12M
ON/OFF
OHCI
EHCI
USB
USB
Clock Controller
Processor
Controller
Clock
Peripherals
ON/OFF
AT91SAM9G45
pck[..]
MCK
periph_clk[..]
SysClk DDR
PCK
int
301
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