AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 778

• Manufacturer Part Number: AT91SAM9G45-EKES
• Description: KIT EVAL FOR AT91SAM9G45
• Manufacturer: Atmel
• Series: AT91SAM Smart ARMr
• Type: MCUr

Specifications of AT91SAM9G45-EKES

• Contents: Board
• Processor To Be Evaluated: SAM9G45
• Data Bus Width: 32 bit
• Interface Type: I2C, SPI, UART
• Maximum Operating Temperature: + 50 C
• Minimum Operating Temperature: - 10 C
• Operating Supply Voltage: 1.8 V to 3.3 V
• For Use With/related Products: AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q4626953

36.8.7
36.8.7.1
6438F–ATARM–21-Jun-10
WRITE_MULTIPLE_BLOCK
One Block per Descriptor
3. Wait for XFRDONE in HSMCI_SR register.
1. Wait until the current command execution has successfully terminated.
2. Program the block length in the card. This value defines the value block_length.
3. Program the block length in the HSMCI configuration register with block_length value.
4. Program HSMCI_DMA register with the following fields:
5. Issue a WRITE_MULTIPLE_BLOCK command.
6. Program the DMA Controller to use a list of descriptors. Each descriptor transfers one
a. Read the channel Register to choose an available (disabled) channel.
b. Clear any pending interrupts on the channel from the previous DMA transfer by
c. Program the channel registers.
d. The DMAC_SADDRx register for channel x must be set with the starting address of
e. The DMAC_DADDRx register for channel x must be word aligned.
f.
g. Program DMAC_CTRLBx register for channel x with the following field’s values:
h. Program DMAC_CFGx register for channel x with the following field’s values:
a. Check that CMDRDY and NOTBUSY are asserted in HSMCI_SR.
– OFFSET field with dma_offset.
– CHKSIZE is user defined.
– DMAEN is set to true to enable DMAC hardware handshaking in the HSMCI. This bit
block of data. Block n of data is transferred with descriptor LLI(n).
was previously set to false.
reading the DMAC_EBCISR register.
the HSMCI_FIFO address.
Program DMAC_CTRLAx register of channel x with the following field’s values:
–DST_WIDTH is set to WORD
–SRC_WIDTH is set to WORD
–SCSIZE must be set according to the value of HSMCI_DMA.CHKSIZE Field.
–BTSIZE is programmed with CEILING(block_length/4).
–DST_INCR is set to INCR
–SRC_INCR is set to INCR
–FC field is programmed with peripheral to memory flow control mode.
–both DST_DSCR and SRC_DSCR are set to 1. (descriptor fetch is disabled)
–DIF and SIF are set with their respective layer ID. If SIF is different from DIF, the
–FIFOCFG defines the watermark of the DMA channel FIFO.
–SRC_H2SEL is set to true to enable hardware handshaking on the destination.
–SRC_PER is programmed with the hardware handshaking ID of the targeted
–Enable Channel x writing one to DMAC_CHER[x]. The DMAC is ready and
DMA Controller is able to prefetch data and write HSMCI simultaneously.
HSMCI Host Controller.
waiting for request.
AT91SAM9G45
778