AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 269

• Manufacturer Part Number: AT91SAM9G45-EKES
• Description: KIT EVAL FOR AT91SAM9G45
• Manufacturer: Atmel
• Series: AT91SAM Smart ARMr
• Type: MCUr

Specifications of AT91SAM9G45-EKES

• Contents: Board
• Processor To Be Evaluated: SAM9G45
• Data Bus Width: 32 bit
• Interface Type: I2C, SPI, UART
• Maximum Operating Temperature: + 50 C
• Minimum Operating Temperature: - 10 C
• Operating Supply Voltage: 1.8 V to 3.3 V
• For Use With/related Products: AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q4626953

22.7.7
Name:
Access:
Reset:
• LPCB: Low-power Command Bit
Reset value is “00”.
00 = Low-power Feature is inhibited: no power-down, self refresh and Deep power mode are issued to the SDRAM device.
01 = The DDRSDRC issues a Self Refresh Command to the SDRAM device, the clock(s) is/are de-activated and the CKE
signal is set low. The SDRAM device leaves the self refresh mode when accessed and enters it after the access.
10 = The DDRSDRC issues a Power-down Command to the SDRAM device after each access, the CKE signal is set low.
The SDRAM device leaves the power-down mode when accessed and enters it after the access.
11 = The DDRSDRC issues a Deep Power-down Command to the Low-power SDRAM device.This mode is unique to
Low-power SDRAM devices.
• CLK_FR: Clock Frozen Command Bit
Reset value is “0”.
This field sets the clock low during power-down mode or during deep power-down mode. Some SDRAM devices do not
support freezing the clock during power-down mode or during deep power-down mode. Refer to the SDRAM device
datasheet for details on this.
1 = Clock(s) is/are frozen.
0 = Clock(s) is/are not frozen.
• PASR: Partial Array Self Refresh
Reset value is “0”.
This field is unique to Low-power SDRAM. It is used to specify whether only one quarter, one half or all banks of the
SDRAM array are enabled. Disabled banks are not refreshed in self refresh mode.
The values of this field are dependant on Low-power SDRAM devices.
After the initialization sequence, as soon as PASR field is modified, Extended Mode Register in the external device mem-
ory is accessed automatically and PASR bits are updated. In function of the UPD_MR bit, update is done before entering in
self refresh mode or during a refresh command and a pending read or write access.
6438F–ATARM–21-Jun-10
31
23
15
–
7
–
–
–
DDRSDRC Low-power Register
30
22
14
DDRSDRC_LPR
Read-write
See
–
6
–
–
Table 22-9
PASR
29
21
13
5
–
TIMEOUT
UPD_MR
28
20
12
4
–
27
19
11
3
–
–
DS
CLK_FR
26
18
10
2
–
–
AT91SAM9G45
25
17
9
1
–
–
LPCB
TCR
APDE
24
16
8
0
–
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