AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 194

• Manufacturer Part Number: AT91SAM9G45-EKES
• Description: KIT EVAL FOR AT91SAM9G45
• Manufacturer: Atmel
• Series: AT91SAM Smart ARMr
• Type: MCUr

Specifications of AT91SAM9G45-EKES

• Contents: Board
• Processor To Be Evaluated: SAM9G45
• Data Bus Width: 32 bit
• Interface Type: I2C, SPI, UART
• Maximum Operating Temperature: + 50 C
• Minimum Operating Temperature: - 10 C
• Operating Supply Voltage: 1.8 V to 3.3 V
• For Use With/related Products: AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q4626953

Figure 21-9. No Setup, No Hold On NRD and NCS Read Signals
21.8.1.5
21.8.2
21.8.2.1
194
AT91SAM9G45
Read Mode
Null Pulse
Read is Controlled by NRD (READ_MODE = 1):
NBS0,NBS1,
NBS2,NBS3,
A0, A1
D[31:0]
A[25:2]
MCK
NRD
NCS
Programming null pulse is not permitted. Pulse must be at least set to 1. A null value leads to
unpredictable behavior.
As NCS and NRD waveforms are defined independently of one other, the SMC needs to know
when the read data is available on the data bus. The SMC does not compare NCS and NRD tim-
ings to know which signal rises first. The READ_MODE parameter in the SMC_MODE register
of the corresponding chip select indicates which signal of NRD and NCS controls the read
operation.
Figure 21-10
read data is available t
NRD. In this case, the READ_MODE must be set to 1 (read is controlled by NRD), to indicate
that data is available with the rising edge of NRD. The SMC samples the read data internally on
the rising edge of Master Clock that generates the rising edge of NRD, whatever the pro-
grammed waveform of NCS may be.
NCS_RD_PULSE
NRD_CYCLE
NRD_PULSE
shows the waveforms of a read operation of a typical asynchronous RAM. The
PACC
after the falling edge of NRD, and turns to ‘Z’ after the rising edge of
NCS_RD_PULSE
NRD_PULSE
NRD_CYCLE
NCS_RD_PULSE
NRD_CYCLE
NRD_PULSE
6438F–ATARM–21-Jun-10