AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 821

• Manufacturer Part Number: AT91SAM9G45-EKES
• Description: KIT EVAL FOR AT91SAM9G45
• Manufacturer: Atmel
• Series: AT91SAM Smart ARMr
• Type: MCUr

Specifications of AT91SAM9G45-EKES

• Contents: Board
• Processor To Be Evaluated: SAM9G45
• Data Bus Width: 32 bit
• Interface Type: I2C, SPI, UART
• Maximum Operating Temperature: + 50 C
• Minimum Operating Temperature: - 10 C
• Operating Supply Voltage: 1.8 V to 3.3 V
• For Use With/related Products: AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q4626953

37.4
37.4.1
37.5
37.5.1
6438F–ATARM–21-Jun-10
Product Dependencies
I/O Lines
I/O Lines
Power Management
Access to the USB host operational registers is achieved through the AHB bus slave interface.
The Open HCI host controller and Enhanced HCI host controller initialize master DMA transfers
through the AHB bus master interface as follows:
Memory access errors (abort, misalignment) lead to an “Unrecoverable Error” indicated by the
corresponding flag in the host controller operational registers.
The USB root hub is integrated in the USB host. Several USB downstream ports are available.
The number of downstream ports can be determined by the software driver reading the root
hub’s operational registers. Device connection is automatically detected by the USB host port
logic.
USB physical transceivers are integrated in the product and driven by the root hub’s ports.
Over current protection on ports can be activated by the USB host controller. Atmel’s standard
product does not dedicate pads to external over current protection.
HFSDPs, HFSDMs, HHSDPs and HHSDMs are not controlled by any PIO controllers. The
embedded USB High Speed physical transceivers are controlled by the USB host controller.
HFSDPs, HFSDMs, HHSDPs and HHSDMs are not controlled by any PIO controllers. The
embedded USB High Speed physical transceivers are controlled by the USB host controller.
One transceiver is shared with USB Device (UDP) High Speed. In this case USB Host High
Speed Controller uses only Port A, ie, the signals HFSDPA, HFSDMA, HHSDPA and HHSDMA.
The port B is driven by the UDP High Speed, the output signals are DFSDP, DFSDM, DHSDP
and DHSDM.
The transceiver is automatically selected for Device operation once the UDP High Speed is
enabled.
The USB Host High Speed requires a 48 MHz clock for the embedded High-speed transceivers.
This clock is provided by the UTMI PLL, it is UPLLCK.
In case power consumption is saved by stopping the UTMI PLL, high-speed operations are not
possible. Nevertheless, OHCI Full-speed operations remain possible by selecting PLLACK as
the input clock of OHCI.
The High-speed transceiver returns a 30 MHz clock to the USB Host controller.
The USB Host controller requires 48 MHz and 12 MHz clocks for OHCI full-speed operations.
These clocks must be generated by a PLL with a correct accuracy of ± 0.25% thanks to USBDIV
field.
• Fetches endpoint descriptors and transfer descriptors
• Access to endpoint data from system memory
• Access to the HC communication area
• Write status and retire transfer descriptor
AT91SAM9G45
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