AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 600
AT91SAM9G45-EKES
Manufacturer Part Number
AT91SAM9G45-EKES
Description
KIT EVAL FOR AT91SAM9G45
Manufacturer
Atmel
Series
AT91SAM Smart ARMr
Type
MCUr
Datasheets
1.AT91SAM9G45-EKES.pdf
(56 pages)
2.AT91SAM9G45-EKES.pdf
(1218 pages)
3.AT91SAM9G45-EKES.pdf
(66 pages)
Specifications of AT91SAM9G45-EKES
Contents
Board
Processor To Be Evaluated
SAM9G45
Data Bus Width
32 bit
Interface Type
I2C, SPI, UART
Maximum Operating Temperature
+ 50 C
Minimum Operating Temperature
- 10 C
Operating Supply Voltage
1.8 V to 3.3 V
For Use With/related Products
AT91SAM9G45
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
Q4626953
- Current page: 600 of 1218
- Download datasheet (19Mb)
33.7.8.6
Figure 33-41. Header Reception
6438F–ATARM–21-Jun-10
te RSTSTA=1
Baud Rate
US_LINIR
in US_CR
LINBK
LINID
Clock
RXD
Header Reception (Slave Node Configuration)
All the LIN Frames start with a header which is sent by the master node and consists of a Synch
Break Field, Synch Field and Identifier Field.
In Slave node configuration, the frame handling starts with the reception of the header.
The USART uses a break detection threshold of 11 nominal bit times at the actual baud rate. At
any time, if 11 consecutive recessive bits are detected on the bus, the USART detects a Break
Field. As long as a Break Field has not been detected, the USART stays idle and the received
data are not taken in account.
When a Break Field has been detected, the flag LINBK in the Channel Status register
(US_CSR) is set to “1” and the USART expects the Synch Field character to be 0x55. This field
is used to update the actual baud rate in order to stay synchronized (see
received Synch character is not 0x55, an Inconsistent Synch Field error is generated (see
tion
After receiving the Synch Field, the USART expects to receive the Identifier Field.
When the Identifier Field has been received, the flag LINID in the Channel Status register
(US_CSR) is set to “1”. At this moment the field IDCHR in the LIN Identifier register (US_LINIR)
is updated with the received character. The Identifier parity bits can be automatically computed
and checked (see
STA at “1” in the Control register (US_CR).
13 dominant bits (at 0)
33.7.8.13).
Break Field
Section
1 recessive bit
Delimiter
Break
(at 1)
33.7.8.8).The flags LINID and LINBK are reset by writing the bit RST-
Start
Bit
1
0
Synch Byte = 0x55
1
0
1
0
1
0
Stop
Bit
Start
Bit
ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7
AT91SAM9G45
Section
33.7.8.7). If the
Stop
Bit
Sec-
600
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