AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 999

• Manufacturer Part Number: AT91SAM9G45-EKES
• Description: KIT EVAL FOR AT91SAM9G45
• Manufacturer: Atmel
• Series: AT91SAM Smart ARMr
• Type: MCUr

Specifications of AT91SAM9G45-EKES

• Contents: Board
• Processor To Be Evaluated: SAM9G45
• Data Bus Width: 32 bit
• Interface Type: I2C, SPI, UART
• Maximum Operating Temperature: + 50 C
• Minimum Operating Temperature: - 10 C
• Operating Supply Voltage: 1.8 V to 3.3 V
• For Use With/related Products: AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q4626953

6438F–ATARM–21-Jun-10
Note:
Note:
3. Write the starting destination address in the DMAC_DADDRx register for channel x.
4. Write the channel configuration information into the DMAC_CFGx register for channel
5. Make sure that all LLI.DMAC_CTRLBx register locations of the LLI (except the last) are
6. Make sure that the LLI.DMAC_DSCRx register locations of all LLIs in memory (except
7. Make sure that the LLI.DMAC_SADDRx register location of all LLIs in memory point to
8. Make sure that the LLI.DMAC_CTRLAx.DONE field of the LLI.DMAC_CTRLAx register
9. If source picture-in-picture is enabled (DMAC_CTRLBx.SPIP is enabled), program the
10. If destination picture-in-picture is enabled (DMAC_CTRLBx.DPIP is enabled), program
11. Clear any pending interrupts on the channel from the previous DMAC transfer by read-
12. Program the DMAC_CTRLAx, DMAC_CTRLBx and DMAC_CFGx registers according
13. Program the DMAC_DSCRx register with DMAC_DSCRx(0), the pointer to the first
14. Finally, enable the channel by writing a ‘1’ to the DMAC_CHER.ENABLE[n] bit. The
15. The DMAC fetches the first LLI from the location pointed to by DMAC_DSCRx(0).
16. Source and destination requests single and chunk DMAC transactions to transfer the
17. Once the buffer of data is transferred, the DMAC_CTRLAx register is written out to sys-
– v. Incrementing/decrementing or fixed address for source in SRC_INCR field.
– vi. Incrementing/decrementing or fixed address for destination DST_INCR field.
x.
a. Designate the handshaking interface type (hardware or software) for the source
b. If the hardware handshaking interface is activated for the source or destination
set as shown in Row 2 of
ter of the last Linked List item must be set as described in Row 1 of
41-5 on page 981
the last) are non-zero and point to the next Linked List Item.
the start source buffer address proceeding that LLI fetch.
locations of all LLIs in memory is cleared.
DMAC_SPIPx register for channel x.
the DMAC_DPIPx register for channel x.
ing the interrupt status register.
to Row 2 as shown in
Linked List item.
transfer is performed. Make sure that bit 0 of the DMAC_EN register is enabled.
buffer of data (assuming non-memory peripherals). The DMAC acknowledges at the
completion of every transaction (chunk and single) in the buffer and carry out the buffer
transfer
tem memory at the same location and on the same layer (DMAC_DSCRx.DSCR_IF)
where it was originally fetched, that is, the location of the DMAC_CTRLAx register of
The values in the LLI.DMAC_DADDRx register location of each Linked List Item (LLI) in memory,
although fetched during an LLI fetch, are not used.
The LLI.DMAC_SADDRx, LLI.DMAC_DADDRx, LLI.DMAC_DSCRx and LLI.DMAC_CTRLA/Bx
registers are fetched. The LLI.DMAC_DADDRx register location of the LLI although fetched is not
used. The DMAC_DADDRx register in the DMAC remains unchanged.
and destination peripherals. This is not required for memory. This step requires pro-
gramming the SRC_H2SEL/DST_H2SEL bits, respectively. Writing a ‘1’ activates
the hardware handshaking interface to handle source/destination requests for the
specific channel. Writing a ‘0’ activates the software handshaking interface to han-
dle source/destination requests.
peripheral, assign handshaking interface to the source and destination peripherals.
This requires programming the SRC_PER and DST_PER bits, respectively.
shows a Linked List example with two list items.
Table 41-2 on page 982
Table 41-2 on page
982, while the LLI.DMAC_CTRLBx regis-
AT91SAM9G45
Table
41-2.
Figure
999