AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 198

KIT EVAL FOR AT91SAM9G45

AT91SAM9G45-EKES

Manufacturer Part Number
AT91SAM9G45-EKES
Description
KIT EVAL FOR AT91SAM9G45
Manufacturer
Atmel
Series
AT91SAM Smart ARMr
Type
MCUr

Specifications of AT91SAM9G45-EKES

Contents
Board
Processor To Be Evaluated
SAM9G45
Data Bus Width
32 bit
Interface Type
I2C, SPI, UART
Maximum Operating Temperature
+ 50 C
Minimum Operating Temperature
- 10 C
Operating Supply Voltage
1.8 V to 3.3 V
For Use With/related Products
AT91SAM9G45
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
Q4626953
21.8.4
21.8.4.1
Figure 21-14. WRITE_MODE = 1. The write operation is controlled by NWE
21.8.4.2
198
AT91SAM9G45
Write Mode
Write is Controlled by NWE (WRITE_MODE = 1):
Write is Controlled by NCS (WRITE_MODE = 0)
NWR0, NWR1,
NWR2, NWR3
NBS0, NBS1,
NBS2, NBS3,
A0, A1
A
D[31:0]
NWE,
[25:2]
MCK
NCS
The WRITE_MODE parameter in the SMC_MODE register of the corresponding chip select indi-
cates which signal controls the write operation.
Figure 21-14
put on the bus during the pulse and hold steps of the NWE signal. The internal data buffers are
turned out after the NWE_SETUP time, and until the end of the write cycle, regardless of the
programmed waveform on NCS.
Figure 21-15
put on the bus during the pulse and hold steps of the NCS signal. The internal data buffers are
turned out after the NCS_WR_SETUP time, and until the end of the write cycle, regardless of
the programmed waveform on NWE.
shows the waveforms of a write operation with WRITE_MODE set to 1. The data is
shows the waveforms of a write operation with WRITE_MODE set to 0. The data is
6438F–ATARM–21-Jun-10

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