AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 49

• Manufacturer Part Number: AT91SAM9G45-EKES
• Description: KIT EVAL FOR AT91SAM9G45
• Manufacturer: Atmel
• Series: AT91SAM Smart ARMr
• Type: MCUr

Specifications of AT91SAM9G45-EKES

• Contents: Board
• Processor To Be Evaluated: SAM9G45
• Data Bus Width: 32 bit
• Interface Type: I2C, SPI, UART
• Maximum Operating Temperature: + 50 C
• Minimum Operating Temperature: - 10 C
• Operating Supply Voltage: 1.8 V to 3.3 V
• For Use With/related Products: AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q4626953

9.9
9.9.1
Table 9-7.
9.9.2
9.9.3
6438F–ATARM–21-Jun-10
HBurst[2:0]
SINGLE
INCR4
INCR8
WRAP8
Bus Interface Unit
Supported Transfers
Thumb Instruction Fetches
Address Alignment
Supported Transfers
Description
Single transfer
Four-word incrementing burst
Eight-word incrementing burst
Eight-word wrapping burst
The ARM926EJ-S features a Bus Interface Unit (BIU) that arbitrates and schedules AHB
requests. The BIU implements a multi-layer AHB, based on the AHB-Lite protocol, that enables
parallel access paths between multiple AHB masters and slaves in a system. This is achieved by
using a more complex interconnection matrix and gives the benefit of increased overall bus
bandwidth, and a more flexible system architecture.
The multi-master bus architecture has a number of benefits:
The ARM926EJ-S processor performs all AHB accesses as single word, bursts of four words, or
bursts of eight words. Any ARM9EJ-S core request that is not 1, 4, 8 words in size is split into
packets of these sizes. Note that the Atmel bus is AHB-Lite protocol compliant, hence it does not
support split and retry requests.
Table 8 gives an overview of the supported transfers and different kinds of transactions they are
used for.
All instructions fetches, regardless of the state of ARM9EJ-S core, are made as 32-bit accesses
on the AHB. If the ARM9EJ-S is in Thumb state, then two instructions can be fetched at a time.
The ARM926EJ-S BIU performs address alignment checking and aligns AHB addresses to the
necessary boundary. 16-bit accesses are aligned to halfword boundaries, and 32-bit accesses
are aligned to word boundaries.
• It allows the development of multi-master systems with an increased bus bandwidth and a
• Each AHB layer becomes simple because it only has one master, so no arbitration or master-
• The arbitration becomes effective when more than one master wants to access the same
flexible architecture.
to-slave muxing is required. AHB layers, implementing AHB-Lite protocol, do not have to
support request and grant, nor do they have to support retry and split transactions.
slave simultaneously.
Single transfer of word, half word, or byte:
Half-line cache write-back, Instruction prefetch, if enabled. Four-word burst NCNB,
NCB, WT, or WB write.
Full-line cache write-back, eight-word burst NCNB, NCB, WT, or WB write.
Cache linefill
• data write (NCNB, NCB, WT, or WB that has missed in DCache)
• data read (NCNB or NCB)
• NC instruction fetch (prefetched and non-prefetched)
• page table walk read
AT91SAM9G45
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