TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 102

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

Note: Since an interrupt is generated 80 times, the first read to internal RAM (which requires 1 additional state) occurs
Sample 1: Calculation example for CPU + HDMA
Conditions:
Calculation example:
Transfer count
80 times, requiring additional 80 states in total. In addition, from bus REQ to bus ACK, an overhead time of 2
states is also needed for each interrupt request, requiring additional 160 states in total.
follows:
16 (64 bytes/4 bytes = 16 times) and counter B is set to 80.
CPU operation speed (f
I2S sampling frequency : 48 KHz (60 MHz/25/50 = 48 KHz)
I2S data transfer bit length
DMAC channel 0 used to transfer 5 Kbytes from internal RAM to I2S
DMAC source data read time:
DMAC destination write time:
To transfer 5 Kbytes of data in 4-byte units, the transfer count is calculated as
5 Kbytes/4 bytes = 1280 [times]
Since I2S generates an interrupt for every 64 bytes, the DMAC’s counter A is set to
t
HDMA start interval [s] = 1 / I2S sampling frequency [Hz] × (64 / 16 )
CPU bus stop rate = t
STOP
Internal RAM data read time
= 1 state/4 bytes (However, the first 1 byte requires 2 states.)
I2S register write time = 2 states/4 bytes
(HDMA) = (((1 + 2) × 16) × 80) + 80 + 160) / f
STOP
SYS
92CF26A-101
= 68 [μS] / 83.33 [mS] = 0.08 [%]
)
(HDMA) [s] / HDMA start interval [s]
: 60 MHz
: 16 bits
= 83.33 [mS]
SYS
[S] = 68 [μS]
TMP92CF26A
2007-11-21