TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 39

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

releasing Halt
(3) Operation
releasing Halt
Interrupt for
Interrupt for
D0~D31
A0~A23
Figure 3.3.7 Timing chart for IDLE2 Mode Halt state cleared by interrupt
Figure 3.3.8 Timing chart for IDLE1 Mode Halt state cleared by interrupt
a. IDLE2 Mode
b. IDLE1 Mode
D0~D31
A0~A23
WR
RD
WR
RD
X1
IDLE2 Setting Register, can take place. Instruction execution by the CPU stops.
Mode Halt state by an interrupt.
operate. The system clock stops.
system clock; however, clearance of the Halt state (i.e. restart of operation) is
synchronous with it.
an interrupt.
X1
In IDLE2 Mode, only specific internal I/O operations, as designated by the
Figure 3.3.7 illustrates an example of the timing for clearance of the IDLE2
In IDLE1 Mode, only the internal oscillator and the RTC and MLD continue to
In the Halt state, the interrupt request is sampled asynchronously with the
Figure 3.3.8 illustrates the timing for clearance of the IDLE1 Mode Halt state by
Data
Data
92CF26A-38
IDLE2
mode
IDLE1
mode
TMP92CF26A
2007-11-21
Data
Data