TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 74

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

Note:
not based on the interrupt priority level but on the channel number: The lower the
channel number, the higher the priority (Channel 0 thus has the highest priority and
channel 7 the lowest).
destination addresses are 32 bits wide, this type of register can only output 24-bit
addresses. Accordingly, micro DMA can only access 16 Mbytes (The upper 8 bits of a
32-bit address are not valid).
transfers and 4byte transfers. After a transfer in any mode, the transfer source and
transfer destination addresses will either be incremented or decremented, or will
remain unchanged. This simplifies the transfer of data from memory to memory, from
I/O to memory, from memory to I/O, and from I/O to I/O. For details of the various
transfer modes, see section 3.5.2 (4) “Detailed description of the transfer mode
register”.
operations can be performed per interrupt source (Provided that the transfer counter
for the source is initially set to 0000H).
interrupts shown in the micro DMA start vectors in Table 3.5.1 and a micro DMA soft
start.
Destination Address INC Mode (micro DMA transfers are the same in every mode
except Counter Mode). (The conditions for this cycle are as follows: both source and
destination memory are internal-RAM and multiple of 4 numbered source and
destination addresses).
Don’t start any micro DMAs by one interrupt. If any micro DMA are set by it, micro DMA that channel
number is biggest (priority is lowest) is not started.(Because interrupt flag is cleared by micro DMA that
priority is highest)
If micro DMA requests are set simultaneously for more than one channel, priority is
Although the control registers used for setting the transfer source and transfer
Three micro DMA transfer modes are supported: 1byte transfer, 2byte (One word)
Since a transfer counter is a 16-bit counter, up to 65536 micro DMA processing
Micro DMA processing can be initiated by any one of 48 different interrupts – the 47
Figure 3.5.2 shows a 2-byte transfer carried out using a micro DMA cycle in Transfer
States (1) and (2): Instruction fetch cycle (Prefetches the next instruction code)
State (3): Micro DMA read cycle.
State (4): Micro DMA writes cycle.
State (5): (The same as in state (1), (2).)
A23 to A0
Note: In fact, src and dst address are not outputted to A23-A0 pins
because they are internal RAM address.
f
Figure 3.5.2 Timing for micro DMA cycle
SYS
1 state
(1)
92CF26A-73
(2)
(3)
src
(4)
dst
(5)
TMP92CF26A
2007-11-21