TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 716

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

Symbol
SDCISR
SDCMM
SDRCR
SDACR
SDBLS
(5) SDRAM controller
SDRAM
access
control
register
SDRAM
Command
Interval
Setting
Register
SDRAM
refresh
control
register
SDRAM
command
register
SDRAM
HDRAM
burst length
register
Name
Address
0250H
0251H
0252H
0253H
0254H
Read
data shift
function
0: Disable
1: Enable
Always
write “0”
SRDS
R/W
7
1
−
0
TMRD
0: 1 CLK
1: 2 CLK
Always
write “0”
STMRD
6
−
0
1
92CF26A-715
TWR
0: 1 CLK
1: 2 CLK
Address multiplex
type
00: Type A (A9- )
01: Type B (A10- )
10: Type C (A11- )
11: Reserved
For
HDMA5
HDMA burst length
0:1 Word Read / Single Write
1:Full Page Read / Burst Write
SMUXW1 SMUXW0
SDBL5
STWR
R/W
5
0
1
0
TRP
0: 1 CLK
1: 2 CLK
Self
Refresh
auto
exit
function
0:Disable
1:Enable
For
HDMA4
SDBL4
STRP
SSAE
4
0
1
1
0
TRCD
0: 1 CLK
1: 2 CLK
Read/Write
commands
0: Without
auto pre-
charge
1: With auto
Refresh interval
000: 47 states
001: 78 states
010: 156 states 110: 936 states
011: 312 states
For
HDMA3
SDBL3
STRCD
precharge
SRS2
SPRE
R/W
1
0
0
3
0
TRC
000: 1 CLK
001: 2 CLK
010: 3 CLK
011: 4 CLK
Command issue
000: Don’t care
001: Initialization sequence
010: Precharge All command
100: Reserved
101: Self Refresh Entry command
110: Self Refresh Exit command
Others: Reserved
For
HDMA2
SCMM2
SDBL2
STRC2
SRS1
a. Precharge All command
b. Eight Auto Refresh commands
c. Mode Register Set command
R/W
1
0
0
0
100: 468 states
101: 624 states
2
111: 1248 states
For
HDMA1
SCMM1
STRC1
SDBL1
100: 5 CLK
101: 6 CLK
110: 7 CLK
111: 8 CLK
SRS0
R/W
1
0
0
0
0
TMP92CF26A
2007-11-21
SDRAM
controller
0: Disable
1: Enable
Auto
Refresh
0:Disable
1:Enable
For
HDMA0
SCMM0
STRC0
SDBL0
SMAC
SRC
R/W
0
0
0
0
0
0