TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 632

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

3.24.3
Note1: If the disable control is used, set the disable code (B1H) to WDCR after write the clear code (4EH) once.
Note2: If the watchdog timer setting is changed, change setting after setting to disable condition once.
(1) Watchdog timer mode registers (WDMOD)
(2) Watchdog timer control register (WDCR)
Control Registers
The watchdog timer (WDT) is controlled by two control registers WDMOD and WDCR.
(Please refer to setting example.)
1.
2.
3.
This register is used to disable and clear the binary counter for the watchdog timer.
writing the disable code (B1H) to the WDCR register.
(4EH) to the WDCR register.
• Disable control
• Enable control
• Watchdog timer clear control
WDCR
WDMOD
WDCR
WDCR
when detecting runaway.
approximately 65,536.)
timer.
the disable code (B1H) to the watchdog timer control register (WDCR). This
makes it difficult for the watchdog timer to be disabled by runaway.
the enabled state merely by setting <WDTE> to “1”.
RESET terminal internally. Since WDMOD<RESCR> is initialized to 0 at reset, a
reset by the watchdog timer will not be performed.
Setting the detection time for the watchdog timer in <WDTP1:0>
Watchdog timer enable/disable control register <WDTE>
Watchdog timer out reset connection <RESCR>
The watchdog timer can be disabled by clearing WDMOD<WDTE> to 0 and then
Set WDMOD<WDTE> to “1”.
To clear the binary counter and cause counting to resume, write the clear code
This 2-bit register is used for setting the watchdog timer interrupt time used
On a reset this register is initialized to WDMOD<WDTP1:0> = 00.
The detection time for WDT is 2
At reset, the WDMOD<WDTE> is initialized to “1”, enabling the watchdog
To disable the watchdog timer, it is necessary to clear this bit to “0” and to write
However, it is possible to return the watchdog timer from the disabled state to
This register is used to connect the output of the watchdog timer with the
← 0
← 0
← 1
← 0
1
−
0
1
0
−
1
0
92CF26A-631
X
0
1
0
X
1
0
1
1
−
0
1
1
−
0
1
0
0
1
0
15
/f
IO
Write the clear code (4EH).
Clear WDMOD <WDTE> to “0”.
Write the disable code (B1H).
Write the clear code (4EH).
[s]. (The number of system clocks is
TMP92CF26A
2007-11-21