TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 187

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

MAMR2
(014AH)
MAMR1
(0146H)
MAMR0
(0142H)
MSAR3
(014FH)
Note: After reset, only the control register for the CS2 space is effective. The control register for the CS2 space has
The CS2 and CS3 block sizes can vary from 32 Kbytes to 8 Mbytes
The CS0 block size can vary from 256 Bytes to 2 Mbytes
The CS1 block size can vary from 256 Bytes to 4 Mbytes
(b) Memory Address Mask Registers
Bit Symbol
Read/Write
Reset State
Function
Bit Symbol
Read/Write
Reset State
Function
Bit Symbol
Read/Write
Reset State
Function
the B2M bit. If the B2M bit is cleared to 0, the address range between 000000H and FFFFFFH is defined as the
CS2 space. (The B2M bit is cleared to 0after reset.) By setting the B2CSH<B2M> bit to 1, the start address
and the block size can be arbitrarily specified, as in the other spaces.
used to determine the sizes of the CS0 to CS3 spaces by setting particular bits in
MAMR0 to MAMR3 to mask the corresponding start address bits. The address
compare logic uses only the address bits that are not masked (i.e., mask bit cleared to 0)
to detect an address match in the CS0 to CS3 spaces. The upper bits are always
compared.
to CS3 spaces as follows:
Figure 3.8.3 shows the Memory Address Mask registers. MAMR0 to MAMR3 are
Also, the address bits that can be masked by MAMR0 to MAMR3 differ between CS0
CS0 space: A20 to A8
CS1 space: A21 to A8
CS2 and CS3 spaces: A22 to A15
Accordingly, the block size that can be assigned to each space is also different.
Memory Address Mask Register (for CS2 and CS3 spaces)
Memory Address Mask Register (for CS0 space)
Memory Address Mask Register (for CS1 space)
V21
V22
V20
Figure 3.8.3 Memory Address Mask Registers
7
7
1
7
1
1
CS2 or CS3 block size 0: The address compare logic uses this address bit.
CS1 block size 0: The address compare logic uses this address bit
CS0 block size 0: The address compare logic uses this address bit
V20
V21
V19
6
6
6
1
1
1
92CF26A-186
V19
V20
V18
5
5
5
1
1
1
V18
V19
V17
4
4
4
1
1
1
R/W
R/W
R/W
V17
V18
V16
3
3
3
1
1
1
V16
V17
V15
2
2
1
2
1
1
V15 ∼ 9
V14 ∼ 9
V16
1
1
1
1
1
1
TMP92CF26A
2007-11-21
V15
V8
V8
0
0
1
1
0
1