TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 388

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

Endpoint0
(0780H)
Endpoint1
(0781H)
Endpoint2
(0782H)
Endpoint3
(0783H)
bit Symbol
Read/Write
Reset State
bit Symbol
Read/Write
Reset State
bit Symbol
Read/Write
Reset State
bit Symbol
Read/Write
Reset State
3.16.3.2 EPx_FIFO Register (x: 0 to 3)
Note: Read or write to these window registers using 1-byte load instructions only, since each register has only a 1-
EP1_DATA7 EP1_DATA6 EP1_DATA5 EP1_DATA4 EP1_DATA3 EP1_DATA2 EP1_DATA1 EP1_DATA0
EP2_DATA7 EP2_DATA6 EP2_DATA5 EP2_DATA4 EP2_DATA3 EP2_DATA2 EP2_DATA1 EP2_DATA0
EP3_DATA7 EP3_DATA6 EP3_DATA5 EP3_DATA4 EP3_DATA3 EP3_DATA2 EP3_DATA1 EP3_DATA0
byte address. Do not use load instructions of 2 bytes or 4 bytes.
EP0_DATA7 EP0_DATA6 EP0_DATA5 EP0_DATA4 EP0_DATA3 EP0_DATA2 EP0_DATA1 EP0_DATA0
defined by the endpoint descriptor for each endpoint automatically. By this means,
each endpoint is automatically set to each voluntary direction.
Undefined
Undefined
Undefined
8-byte registers:
wLength_L and wLength_H. These are updated whenever a new SETUP token is
received from the host.
the new device request has been received.
request received.
the
STANDARD_REQUEST_FLAG and REQUEST_FLAG.
Undefined
This register is prepared for each endpoint independently.
This is the window register from or to FIFO RAM.
In the auto bus enumeration, the request controller in UDC sets the mode, which is
The device request that is received from the USB host is stored in the to following
bmRequestType,
When the UDC receives without error, INT_SETUP interrupt is asserted, meaning
There is also request which is operated automatically by the UDC, depending on the
In that case, the UDC does not assert the INT_SETUP interrupt. Any request which
R/W
R/W
R/W
R/W
7
7
7
7
UDC
Undefined
Undefined
Undefined
Undefined
R/W
R/W
R/W
R/W
6
6
6
6
is
currently
bRequest,
Undefined
Undefined
Undefined
Undefined
R/W
R/W
R/W
R/W
5
5
5
5
92CF26A-387
Undefined
Undefined
Undefined
Undefined
operating
wValue_L,
R/W
R/W
R/W
R/W
4
4
4
4
Undefined
Undefined
Undefined
Undefined
R/W
R/W
R/W
R/W
3
3
3
can
3
wValue_H,
be
Undefined
Undefined
Undefined
Undefined
R/W
R/W
R/W
R/W
2
2
2
2
checked
wIndex_L,
Undefined
Undefined
Undefined
Undefined
R/W
R/W
R/W
R/W
1
1
1
1
TMP92CF26A
by
2007-11-21
wIndex_H,
Undefined
Undefined
Undefined
Undefined
reading
R/W
R/W
R/W
R/W
0
0
0
0