TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 376

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

3.16.2.3 USBINTFRn, MRn Register
Note 1: The “INTUSB generated number” and “bit number which is set to flag register” are not always equal. In the
Note 2: Disable INTUSB (write 00H to INTEUSB register) before writing to USBINTMRn or USBINTFRn.
Mask register
Interrupt source
(Set by rising edge)
Flag register
Writing “0” to flag register
INTUSB interrupt routine, clear FLAG register (USBINTFRn) after checking it. The interrupt request flag,
which occurrs between the INTUSB interrupt routine and flag register (USBINTFRn) read, is kept in the
interrupt controller.
Therefore, after returning from the interrupt routine, the CPU jumps to INTUSB interrupt routine again.
Software support is required to avoid ending in an error routine when none of the bits in the flag register
(USBINTFRn) is set to “1”.
sources output by the UDC.
INTUSB routine, execute operations according to generated interrupt source after
checking USBINTFRn.
These SFRs control the INTUSB (only one interrupt to CPU) using the 23 interrupt
The USBINTMRn are mask registers and the USBINTFRn are flag registers. In the
The common specification for all MASK and FLAG registers is shown below.
A: The flag register is not set because mask register = “1”.
B: The flag register is not set because interrupt souce changes “1” → “0”.
C: The flag register is set because mask register = “0” and interrupt souce changes “0” → “1”.
D: The flag register is reset to “0” by writing “0” to flag register.
(
Common specifications for all mask and flag registers.)
92CF26A-375
A
B
C
D
TMP92CF26A
2007-11-21