TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 237
TMP92CF26AXBG
Manufacturer Part Number
TMP92CF26AXBG
Description
Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
Manufacturer
Toshiba
Datasheet
1.TMP92CF26AXBG.pdf
(767 pages)
Specifications of TMP92CF26AXBG
Processor Series
TLCS-900
Core
900/H
Data Bus Width
16 bit
Program Memory Type
ROM
Program Memory Size
8 KB
Data Ram Size
144 KB
Interface Type
I2C, I2S, UART, USB
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
136
Number Of Timers
10
Maximum Operating Temperature
+ 50 C
Mounting Style
SMD/SMT
Package / Case
FBGA-228
Development Tools By Supplier
BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
Minimum Operating Temperature
0 C
On-chip Adc
10 bit, 6 Channel
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TMP92CF26AXBG
Manufacturer:
TOSHIBA
Quantity:
4 000
Part Number:
TMP92CF26AXBG
Manufacturer:
TOSHIBA/东芝
Quantity:
20 000
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SDRCR
(0252H)
CPU
60MHz
|
|
625 KHz (10MHz/16)
f
SDRAM controller
SYS
SDRAM state
internal state
Bit symbol
Read/Write
Reset State
Function
Figure 3.10.8 Execution Flow for Executing HALT Instruction after Clock Gear Down
Auto-EXIT
Auto Exit
disable
enable
Exit command is executed when SDCMM<SCMM2:0> is set to “110”. It is also executed
automatically in synchronization with HALT mode release. In either of these two cases,
Auto Refresh is performed immediately after the Self Refresh state is exited. Then, Auto
Refresh is executed at specified intervals. Exiting the Self Refresh state clears
SDCMM<SCMM2:0> to “000”.
command in synchronization with HALT release.
command in synchronization with HALT release. The auto exit function should also be
disabled in cases where the SDRAM operation requirements cannot be met as the operation
clock frequency is reduced by clock gear down, as shown in Figure 3.10.8.
Auto Refresh
The Self Refresh state can be exited by the Self Refresh Exit command. The Self Refresh
Setting SDRCR<SSAE> to “1” enables automatic execution of the Self Refresh Exit
Setting SDRCR<SSAE> to “0” disables automatic execution of the Self Refresh Exit
Always
write “0”
ENTRY
R/W
7
−
0
SR
change
CLK
6
Gear down
SDRAM Refresh Control Register
HALT
5
92CF26A-236
HALT mode
Self
Refresh
auto exit
function
0:Disable
1:Enable
Self Refresh
SSAE
Auto Exit
disable
4
1
Interrupt
Refresh interval
000: 47 states
001: 78 states
010: 156 states
011: 312 states
Gear up
SRS2
3
0
change
CLK
SRS1
R/W
EXIT
SR
2
0
100: 468 states
101: 624 states
110: 936 states
111: 1248 states
Auto-EXIT
SRS0
enable
1
0
Auto Refresh
Auto
Refresh
0:Disable
1:Enable
TMP92CF26A
SRC
Auto Exit
0
0
enable
2007-11-21
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