TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 447

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

3.16.7
Bus Interface and Access to FIFO
(1) CPU bus interface
single packet mode, FIFO capacity that is implemented by hardware is used as large
FIFO. In dual packet mode, FIFO capacity is divided into two and used as two FIFOs.
It is also used as an independent FIFO. Even if the UDC is transmitting and
receiving to USB host, it can be used as an efficient bus by possible load to FIFO.
to “0”, FIFO register runs in single mode.
Sample: Where endpoint 1 is used to dual packet of payload 64 bytes.
The UDC prepares two types of FIFO access, single packet and dual packet. In
But control transfer type receives only single packet mode.
Epx_SINGLE signal in dual packet mode must be fixed to “0”. If this signal is fixed
EP1_FIFO size
EP1_SINGLE signal
EP1 Descriptor setting
Direction
Max payload size
Transfer mode
92CF26A-446
:
:
:
:
:
Prepare 128 bytes
Hold 0
Optional
64 bytes
Optional
TMP92CF26A
2007-11-21