TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 360

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

Note: If the software reset is executied , operation selection is reset, and its mode is set to port mode from I
(14)
(15)
(16)
(17)
by external noises, etc.
An internal Reset signal pulse can be generated by setting SBICR2<SWRST1:0> to
“10” and “01”. This initializes the SBI circuit internally. All command registers and
status registers are initialized as well.
initialized.
writing the SBIDBR.
In the master mode, after the start condition is generated the slave address and the
direction bit are set in this register.
a slave device.
The slave address output from the master device is recognized by setting the
I2CAR<ALS> to “0”. The data format is the addressing format. When the slave
address is not recognized at the <ALS> = “1”, the data format is the free data format.
Therefore, setting <I2SBI> is necessary before the HALT instruction is executed.
SBICR1<SWRMON>is automatically set to “1” after the SBI circuit has been
Software Reset function
Serial Bus Interface Data Buffer Register (SBIDBR)
I
Setting register for IDLE2 mode operation (SBIBR0)
The software Reset function is used to initialize the SBI circuit, when SBI is rocked
The received data can be read and transferred data can be written by reading or
I2CAR<SA6:0> is used to set the slave address when the TMP92CF26A functions as
SBIBR0<I2SBI> is the register setting operation/stop during IDLE2-mode.
2
CBUS Address Register (I2CAR)
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TMP92CF26A
2007-11-21
2
C mode.