TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 579

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

LCDLDDLY<PDT> = 0
LLOAD
LCP0
LD17-LD0
LD17-LD0
LVSYNC
LHSYNC
LHSYNC
LLOAD
TFT-2(TFT panel: 240com x 320seg by SH company) (f
ld
ld
ld
ld
ld
ldw
ldw
ld
ld
ld
ld
ld
ld
ldl
set
(lcdmode0),3dh
(lcdmode1),00h
(lcdsize),75h
(lcdctl0),00h
(lcdctl1),061h
(lcdhsp),340
(lcdvsp),252
(lcdprvsp),7
(lcdhsdly),11
(lcdlddly),16
(lcdhsw),2
(lcdldw),64
(lcdhwb8),02h
(lsaml),400000h
0,(lcdctl0)
11LCP0
1
16LCP0
3LCP0
2
92CF26A-578
1
8
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
341LCP0
2
VRAM: In-RAM, f
320seg,240com
PIP-OFF, Divide Frame-OFF
LCP0 posedge, LHSYNC negedge, LVSYNC negedge, LLOAD
posedge
LVSYNC enable width=LHSYNC*2
LHSYNC cycle(LCP0*341)
LVSYNC cycle(LHSYNC*253)
Frame Rate=12.5ns*16*341*253 (58Hz)
Vertical front porch 7
LHSYNC delay=11*LCP0
LLOAD delay=16*LCP0 ,<PDT>=0
LHSYNC enable width=3*LCP0
LLOAD enable width=320*LCP0
<LDW8>=1
main area start address set
LCDC start
3
320LCP0
SYS
*16-clk, TFT256K color
SYS
=80MHz)
320
5LCP0
253
TMP92CF26A
2007-11-21
1