TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 547

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

LCDLDDLY
(0290H)
LCDCTL1
(0286H)
LLDP=0
LLDP=1
Note: The delay time for the LLOAD signal is controlled based on LCDLDDLY<PDT>=1. Therefore, even if the delay
bit Symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
inserted in the LLOAD signal.
As shown in the diagram below, delay time of 0 to 127 pulses of the LCP0 clock can be
Delay time = <LDD6:0>
Signal Name
LCP0 signal
LLVSYNC signal
LHSYNC signal
(Internal reference signal)
LLOAD signal
Delay control
time is set to”0” with LCDLDDLY<PDT>=0, the LLOAD signal is output with a delay of one LCP0 clock. Be
careful about this point.
<LLDP>.
The phase of the LLOAD signal can be inverted by the setting of LCDCTL1
(Enable width control)
Data output
0: Sync with
1: 1 clock
LCP0
phase
0: Rising
1: Falling
timing
LLOAD
later than
LLOAD
LLOAD period
LCP0P
PDT
R/W
7
0
7
1
LHSYNC
phase
0: Rising
1: Falling
LDD6
LHSP
6
0
6
0
LCD Control 1 Register
LLOAD Delay Register
R/W
(Phase control)
92CF26A-546
LVSYNC
phase
0: Rising
1: Falling
LDD5
5
0
LVSP
5
1
LLOAD signal
LLOAD
phase
0: Rising
1: Falling
LDD4
4
LLDP
0
LLOAD delay (bits 6-0)
4
0
LDD3
W
3
0
3
LDD2
2
0
2
LVSYNC
enable time control
00: 1 clock of LHSYNC
01: 2 clocks of LHSYNC
10: 3 clocks of LHSYNC
11: Reserved
LDD1
LVSW1
1
0
1
0
TMP92CF26A
R/W
2007-11-21
LDD0
LVSW0
0
0
0
0