TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 133

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

P9
(0024H)
P9CR
(0026H)
P9FC
(0027H)
P9FC2
(0025H)
P9DR
(0089H)
P92 setting
<P92F>
<P92FC2>
0
1
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Function
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Function
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Function
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Function
CTS /SCLK0
Note 1: A read-modify-write operation cannot be performed for P9CR, P9FC and P9FC2.
Note 2: When setting P96 pin to INT4 input, set P9DR<P96D> to “0” (prohibit input), and when driving P96 pin to “0”,
Don’t setting
Input port,
Input
0
0
execute HALT instruction. This setting generates INT4 inside. If don’t using external interrupt in HALT
condition, set like an interrupt don’t generated. (e.g. change port setting)
Always
write “0”
Data from external
P97D
P97
7
W
7
7
7
7
−
0
−
1
−
SCLK0 Output
Output port
port
R/W
R
−
1
0:
1: INT4
P96
port
P96D
P96F
6
W
6
6
6
−
6
0
1
−
Input
Figure 3.7.17 Register for Port 9
P91 setting
Input/Output buffer drive register for standby mode
Input
RXD0
Port 9 Function registers 2
Port 9 function register
Port 9 control register
5
Port 9 drive register
port
5
5
5
5
Input
0
92CF26A-132
Port 9 register
<P91C>
Output port
4
4
4
4
4
1
3
3
3
3
3
P90 setting
<P90F>
<P90C>
Refer to
following
table
Always
write “0”
0
1
Data from external port (Output
P92C
P92D
P92F
P92
W
W
2
2
2
0
−
−
0
−
2
1
−
0
−
2
latch register is set to “1”)
Refer to following table
Input port
setting
Don’t
0
P91C
P91D
R/W
R/W
P91
W
1
1
1
1
1
−
−
0
−
1
Output port
0:CMOS
1:Open-drain
Refer to
following
table
Output
TXD0
TMP92CF26A
P90F2
P90C
P90D
P90F
1
P90
W
W
0
0
0
0
1
−
0
0
−
0
−
0
−
2007-11-21