TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 355

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

3.15.5
Control in I
(1)
(2)
(3)
a.
SBICR1<ACK> to “1”, TMP92CF26A operates in the acknowledge mode. The
TMP92CF26A generates an additional clock pulse for an Acknowledge signal when
operating in Master Mode. In the transmitter mode during the clock pulse cycle, the
SDA pin is released in order to receive the acknowledge signal from the receiver. In
the receiver mode during the clock pulse cycle, the SDA pin is set to the Low in order
to generate the acknowledge signal.
TMP92CF26A does not generate a clock pulse for the Acknowledge signal when
operating in the Master Mode.
receiving data.
Since the <BC2:0> is cleared to 000 as a start condition, a slave address and direction
bit transmission are executed in 8 bits. Other than these, the <BC2:0> retains a
specified value.
Acknowledge Mode Specification
Number of transfer bits
Serial clock
t
t
fscl = 1/(t
When slave address is matched or detecting GENERAL CALL, and set the
Clear the <ACK> to “0” for operation in the Non-Acknowledge Mode; The
The SBICR1<BC2:0> is used to select a number of bits for next transmitting and
LOW
HIGH
outputted on the SCL pin in Master Mode. Set a communication baud rates that
meets the I
the equations shown below.
Clock source
= (2
The SBICR1 <SCK2:0> is used to select a maximum transfer frequency
=
= (2
2
C Bus Mode
LOW
n-1
n − 1
2
f
SYS
+ 29)/(f
n
+ 6)/(f
+ 36
+ t
/4
t
HIGH
HIGH
2
SYS
SYS
C bus specification, such as the shortest pulse width of t
)
/4)
/4)
Figure 3.15.8 Clock source
t
LOW
92CF26A-354
SBICR1<SCK2:0>
000
001
010
011
100
101
110
1/fscl
10
n
4
5
6
7
8
9
TMP92CF26A
LOW
2007-11-21
, based on