TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 316

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

Timer output pin TB0OUT0
Count clock
(Prescaler output clock)
TB0IN0 pin input
(External trigger pulse)
Match with TB0RG0H/L
Match with TB0RG1H/L
(4) Application examples of capture function
1.
2.
3.
1.
Used capture function, they can be applied in many ways, for example;
input the external trigger pulse from TB0IN0 pin, and load the value of up
counter into capture register TB0CP0H/L at the rising edge of the TB0IN0 pin.
the TB0CP0H/L value (c) plus a delay time (d) to TB0RG0H/L (=c+d), and set the
above set value (c+d) plus a one-shot pulse width (p) to TB0RG1H/L (=c+d+p).
TB0FF0 inversion is enabled only when the up counter value matches
TB0RG0H/L or TB0RG1H/L. When interrupt INTTB01 occurs, this inversion will
be disabled after one-shot pulse is output.
One-shot pulse output from external trigger pulse
Frequency measurement
Pulse width measurement
One-shot pulse output from external trigger pulse
Set the up counter UC10 in free-running mode with the internal input clock,
When the interrupt INT6 is generated at the rising edge of TB0IN0 input, set
The TB0FFCR<TB0E1T1, TB0E0T1> register should be set “11” and that the
The (c), (d) and (p) correspond to c, d, and p in the Figure 3.13.12.
Figure 3.13.12 One-shot Pulse Output (with delay)
c
Set the counter in free-running mode.
Disable inversion
caused by loading into
TB0CP0H/L
Load to capture registesr 0 (TB0CP0H/L)
INT6 occured
92CF26A-315
Delay time
Inversion
enable
(d)
c + d
Inversion
enable
Pulse width
(p)
c + d + p
INTTB01 occured
TMP92CF26A
2007-11-21