TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 515
TMP92CF26AXBG
Manufacturer Part Number
TMP92CF26AXBG
Description
Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
Manufacturer
Toshiba
Datasheet
1.TMP92CF26AXBG.pdf
(767 pages)
Specifications of TMP92CF26AXBG
Processor Series
TLCS-900
Core
900/H
Data Bus Width
16 bit
Program Memory Type
ROM
Program Memory Size
8 KB
Data Ram Size
144 KB
Interface Type
I2C, I2S, UART, USB
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
136
Number Of Timers
10
Maximum Operating Temperature
+ 50 C
Mounting Style
SMD/SMT
Package / Case
FBGA-228
Development Tools By Supplier
BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
Minimum Operating Temperature
0 C
On-chip Adc
10 bit, 6 Channel
Lead Free Status / Rohs Status
Details
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TMP92CF26AXBG
Manufacturer:
TOSHIBA
Quantity:
4 000
Part Number:
TMP92CF26AXBG
Manufacturer:
TOSHIBA/东芝
Quantity:
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3.18.4
(Example settings) I2S0WS = 8 KHz, I2SnCKO = 400 kHz, data transmission on the rising edge (at f
(Main routine)
INTEI2S01
I2S0CTL
(INTI2S Interrupt Routine)
X: Don't care, −: N o change
PFCR
PFFC
I2S0C
I2S0CTL
I2S0BUF
I2S0BUF
Figure3.18.5 Connection Example between the TMP92CF26A and an External LSI
Note: After reset, PF0 to PF2 are placed in a high-impedance state. Connect each pin with a pull-up or pull-down
Detailed Description of Operation
(1) Connection example
(2) Operation procedure
resistor as necessary.
external LSI (DA converter) using channel 0.
units. Whenever each 64-byte buffer space becomes empty, an INTI2Sn interrupt is
generated. The next data to be transmitted should be written to the FIFO in the
interrupt routine.
Figure3.18.5 shows an example of connections between the TMP92CF26A and an
The I
Example settings and timing diagram are shown below.
2
S unit incorporates a 128-byte FIFO buffer that is divided into two 64-byte
X
X
X
TMP92CF26A
7
−
1
0
0
1
0
*
*
*
*
*
*
*
*
(Transmit)
PF2/I2S0WS
PF0/I2SCKO
X
X
0
X
0
X
X
6
−
1
*
*
*
*
*
*
*
*
PF1/I2SDO
X
X
X
X
5
−
−
−
0
1
*
*
*
*
*
*
*
*
X
4
−
−
−
1
1
0
0
0
*
*
*
*
*
*
*
*
X
X
X
3
−
−
0
0
1
1
*
*
*
*
*
*
*
*
2
0
−
1
1
0
0
0
0
0
*
*
*
*
*
*
*
*
92CF26A-514
1
0
−
1
1
1
0
0
0
0
*
*
*
*
*
*
*
*
0
1
−
1
0
0
1
0
1
0
*
*
*
*
*
*
*
*
WS
CK
DATA
Example: DA converter
(Receive)
Set interrupt level.
Set pins: PF0 (I2S0CKO), PF1 (I2S0DO), PF2 (I2S0WS)
Divider value N=150
Divider value K=50
Set transmit mode (I2S mode, MSB-first, 16-bit).
Falling edge, WS=0 Left, clock stop.
Write left and right data to FIFO (4 bytes × 32 = 128 bytes).
Start transmission.
Write left and right data to FIFO (4 bytes × 16 = 64 bytes).
SYS
TMP92CF26A
= 50 MHz)
2007-11-21
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