TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 489

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

(d) CEN
(e) SPCS_B
(f) UNIT16
(g) FDPXE
(h) TXMOD
(i) TXE
might flow in the SPDI pin, for it enters the floating state. Also, currents may
unintentionally flow into the card from the SPCS , SPCLK and SPDO pins when they
generate a logic 1. This bit can be used to avoid these problems.
SPDI signal, SPDI pin is prohibited to input (avoiding penetrated current) and SPCS ,
SPCLK, SPDO pin become high impedance.
on, as well as that the clock signal is supplied to the SPIC (SPIMD<XEN> = 1).
hereafter refered to as the UNIT. Data transmission or reception must not be
performed while changing the state of this bit
specifies whether to align the transmit and receive data on the UNIT-size boundaries.
this bit.
During transmission, it is prohibited to change the transmission mode from Sequential
to UNIT, or vice versa.
interrupt is generated when the data is loaded from the transmit data register (SPITD)
to the transmit shfit register.
interrupt is generated when the empty space of the FIFO becomes 16 bytes or 32 bytes.
this bit set to 1 after loading the transmit data into the transmit FIFO, or when
loading the transmit data to the transmit FIFO when this bit is already set to 1. The
state of this bit can be changed even during data transmission. If this bit is cleared to 0
during a data transmission, the transmission is stopped after completing the
transmission of the UNIT data currently being transmitted.
This bit enables or disables the pins for the SD card and MMC connections.
When the card is not inserted or when it is not powered on, a shoot through current
If write <CEN> to “0” with PRCR and PRFC selecting SPCS , SPCLK, SPDO and
When writing a 1 to the CEN bit, ensure that a card is properly inserted and powered
This bit specified the logic stateof the SPCS output.
This bit selects the data length for transmission and reception. The data length is
This bit should be set to 1 when performing the full-duplex communication. This bit
Data transmission or reception must not be performed while changing the state of
This bit selects the data transmission mode from UNIT and Sequential modes.
For UNIT-mode transmission, the transmit FIFO buffer is disabled. The TEMP
For sequential-mode transmission, the 32-byte FIFO is enabled. The TEMP
This bit enables or disables data transmission. Data transmission is started when
92CF26A-488
TMP92CF26A
2007-11-21