TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 551

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

LVSYNC
LFR
<FREDGE>=1
<FRMON> = 0
LFR
<FREDGE>=1
<FRMON>= 1
<FMP7:0> = N
<FML7:0> = any
<DLS> = 0
LFR
<FREDGE>=0
<FRMON> = 0
LHSYNC
LFR
<FREDGE>=0
<FRMON>= 1
<FMP7:0> = N
<FML7:0> = any
<DLS> = 0
(5) LFR Signal
Note1: The effect of this function varies with the characteristics of the LCD driver and LCD panel to be used.
Note2: LFR signal delaies synchronous with LHSYNC signal.
Generally, setting a prime number (3, 5, 7, 11, 13 and so on) as the “N” value produces better results.
liquid crystal cells. With small screens in monochrome mode, the polarity of the LFR signal
is normally inverted in synchronization with each screen display. With large screens or
when grayscale or color mode is used, the polarity is inverted at shorter intervals to adjust
the display quality.
at intervals of “LHSYNC x N” (LHSYNC: internal reference signal with 0 delays). The “N”
value is specified in LCDDVM0<FML3:0> and LCDDVM1<FML7:4>.
LHSYNC signal, and when <DLS>="0" and <FREDGE>=1, LFR signal synchronous with
rear edge of LHSYNC signal.
signal is inverted in synchronization with the LVSYNC period.
(The refresh rate is not changed.)
The LFR (frame) signal is used to control the direction of bias the LCD driver applies on
When LCDCTL0<FRMON>=“1” and LCDCTL0<DLS> = “0”, the LFR signal is inverted
When <DLS>= “0” and <FREDGE>= “0”, LFR signal synchronous with front edge of
When LCDCTL0<FRMON> is set to “0” to disable the frame divide function, the LFR
Enabling this function does not affect the waveform and timing of the LVSYNC signal.
N
N
92CF26A-550
TMP92CF26A
2007-11-21