TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 617

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

ADREG3H
(12A7H)
ADREG3L
(12A6H)
ADREG2L
(12A4H)
ADREG2H
(12A5H)
Channel X conversion
result
bit Symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
•
•
•
“1”. When Lower register (ADRECxL) is read, this bit is cleared to “0”.
ADREGxH/L before both the ADREGxH and ADREGxL are read. This bit is cleared to “0” by reading Flag.
Bits 5 ∼ 2 are always read as “0”.
Bit 0 is the AD conversion result store flag <ADRxRF>. When AD conversion result is stored, the flag is set to
Bit 1 is the Overrun flag <OVRx>. This bit is set to “1” if a next conversion result is written to the
Store Lower 2 bits of
Store Lower 2 bits of
ADR21
ADR29
ADR31
ADR39
AN2 AD conversion
AN3 AD conversion
7
7
7
7
0
0
0
0
result
result
R
R
Figure 3.23.7 AD Conversion Registers
AD Conversion Result Register 1 High
AD Conversion Result Register 3 High
AD Conversion Result Register 2 Low
AD Conversion Result Register 3 Low
ADREGxH
ADR20
ADR28
ADR30
ADR38
9
6
6
6
6
7
0
0
0
0
8
6
7
Store Upper 8 bits of AN2 AD conversion result
Store Upper 8 bits of AN3 AD conversion result
5
ADR27
ADR37
92CF26A-616
5
5
5
5
0
0
4
6
3
5
ADR26
ADR36
2
4
4
4
4
4
0
0
1
3
R
R
0
2
ADR25
ADR35
3
3
3
0
3
0
1
7
0
6
ADR24
ADR34
5
2
2
2
2
0
0
4
3
0:No
1: Generate
0:No
1: Generate
Overrun
flag
Overrun
flag
generate
generate
ADR33
ADR23
OVR2
OVR3
2
1
1
1
1
0
0
0
0
ADREGxL
1
TMP92CF26A
R
R
AD
conversion
result store
flag
1: Stored
AD
conversion
result store
flag
1: Stored
ADR2RF
ADR3RF
0
2007-11-21
ADR22
ADR32
0
0
0
0
0
0
0
0