TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 450

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

DATASET = 0
Wait receiving data
DATASET = 1
(b) Dual packet mode
according to priority in hardware. It can be performed at once, transmitting and
receiving data to USB host and exchanges to external of UDC.
packets, and consider the order of priority. If it has received data to two packets,
the UDC outputs from first receiving data by FIFO that can be accessed are
common in two packets. DATASIZE register is prepared for both packet A and
packet B. First, the CPU must recognize the data number of first receiving packet
by PACKET_ACTIVE bit. If PACKET_ACTIVE bit has been set to 1, that packet
is received first. Packet A and packet B set data turn about always.
• Read size of receiving data from relevant endpoint
• There are below 3 cases by setting bit of DATASET
Figure 3.16.17 Receiving Sequence in Dual Packet Mode
In dual packet mode, FIFO is divided into A and B packet, and is controlled
When it reads out data from FIFO for receiving, confirm condition of two
This is shown below.
Only A: Read number of sizeA register
Only B: Read number of sizeB register
Both of A and B: Read number of sizeA + B register
DATASET register
DATASET register
• Clear receiving data in FIFO
• Clear applicable bit in DATASET register
• Check bit of EPx_DSET_A
• Check bit of EPx_DSET_B
SIZE register
• Set bit of EPx_DSET_A (B)
• Assert EPx_DATASET signal
• Confirm Size of SIZE_A_L
• Confirm Size of SIZE_A_H
• Confirm Size of SIZE_B_L
• Confirm Size of SIZE_B_H
92CF26A-449
IDLE
Receiving valid data
Interrupt by EPx_FULL_A (B)
Check DATASET register
TMP92CF26A
2007-11-21