TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 317

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

Example: To output 2ms one-shot pulse with 3ms delay to the external trigger pulse to TB0IN0pin
Main setting
Setting in INTTB01 routine
X: Don't care, −: No change
TB0MOD
TB0FFCR
PPFC
INTE56
INTETB0
TB0RUN
Setting in INT6 routine
TB0RG0
TB0RG1
TB0FFCR
INTETB0
TB0FFCR
INTETB0
value is loaded into capture register (TB0CP0H/L), and set the TB0CP0H/L value (c)
plus the one –shot pulse width (p) to TB0RG1H/L when the interrupt INT6 occurs. The
TB0FF0 inversion should be enabled when the up counter (UC10) value matched
TB0RG1H/L, and disabled when generating the interrupt INTTB01.
When delay time is unnecessary, invert timer flip-flop TB0FF0 when the up counter
← X
← X
←
← X
← X
←
← TB0CP0 + 3ms/φT1
← TB0RG0 + 2ms/φT1
← X
← X
← X
← X
–
–
X
X
1
1
0
0
X
1
X
0
1
0
–
0
0
X
–
0
–
0
0
0
–
0
0
X
–
0
–
0
X
X
X
X
1
0
–
–
1
0
*Clock state
0
0
–
–
0
1
1
0
0
0
92CF26A-316
X
0
1
–
–
0
–
0
–
0
X
1
0
–
0
1
–
0
–
0
System clock :
Prescaler clock :
Load to TB0CP0H/L at the rising edge of TB0IN0
Select PP6 as TB0OUT0 pin (port setting)
Enable INT6
Disable INTTB00, INTTB01
Start TMRB0
Enable INTTB01
Disable INTTB01
Free-running
Count with φT1
Clear TB0FF0 to “0”
Disable TB0FF0 inversion
Enable TB0FF0 inversion when the up counter value
matches TB0RG0H/L or TB0RG1H/L
Disable TB0FF0 inversion when the up counter value
matches TB0RG0H/L or TB0RG1H/L
f
f
SYS
SYS
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TMP92CF26A
2007-11-21