TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 448

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

DATASET = 0
Wait receiving data
DATASET = 1
(a) Single packet mode
Figure 3.16.15 is receiving sequence. Figure 3.16.16 is transmitting sequence.
This chapter focuses on access to FIFO. For Data sequence with USB host refer to
chapter 5.
can be changed between single packet and dual packet by setting Epx_SINGLE
register. Do not change packet when transferring.
Figure 3.16.15 Receiving Sequence in Single Packet Mode
This is data sequence of single packet mode when CPU bus interface is used.
Endpoint 0 cannot be changed to exclusive single packet mode. Endpoints 1 to 3
DATASET register
• Check bit of EPx_DSET_A
SIZE register
RD receiving data of size in relevant
endpoint
• Clear receiving data in FIFO
• Clear relevant bit of DATASET
• Size of SIZE_A_L confirmation
•
DATASET register
• Set bit of EPx_D SET_A
• Assert EPx_DATASET signal
Size of SIZE_A_H confirmation
register
92CF26A-447
IDLE
Receive valid data
Interrupt by EPx_FULLA
Check DATASET register
TMP92CF26A
2007-11-21