TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 439

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

INT_SETUP
INT_ ENDPOINT0
INT_STATUS
REQUEST FLAG
DATASET register
BRD
BWR
SETUP DATA0 ACK
bmRequestType register
bRequest register
wValue register
wIndex register
wLength register
Figure 3.16.11 The Control Flow in UDC (Control Write Transfer Type)
Stage change condition of control write transfer type
These changing conditions are shown in Figure 3.16.11.
1.
2.
3.
correspond with the data number specified by the device request. The CPU can
therefore process using INT_STATUSNAK interrupt. However, when class and
vendor request is used, wLength value corresponds to data transfer number in
data phase. With this setting, using this interrupt is not need. Data stage data
can be confirmed by accessing DATASIZE register.
OUT
• Start setup stage in the UDC.
• Receive data in request normally and judge. And assert INT_SETUP
• Change data stage in the UDC.
• CPU receives a request from the request register every INT_SETUP
• Judge request and access Setup Received register for inform the UDC that
• Receive dataphase data normally, and set EP0 bit of DATASET register.
• The CPU receives data in FIFO by setting DATASET.
• The CPU processes receiving data by device request.
• When the CPU finishes transaction, it writes “0” to EP0 bit of EOP register.
• Change status stage in the UDC.
• Return data packet of 0 data to IN token, and change state to IDLE in the
• Assert INT_STATUS interrupt externally when ACK for 0 data packet is
In control read transfer type, transaction number of data stage does not always
Receive SETUP token from host.
Receive OUT token from host.
Receive IN token from host.
interrupt externally.
interrupt.
INT_SETUP interrupt has been recognized.
UDC.
received.
DATA1
Setup Received register
ACK
OUT
92CF26A-438
DATA0
NAK
EP0_FIFO (RD of payload)
OUT
DATA0
EP0_FIFO (Rest data)
ACK
IN
NAK
IN
TMP92CF26A
EOP register
2007-11-21
DATA1
ACK