TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 485

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

Figure 3.17.4 Timing Diagram of Data Transmissions Controlled by the TCPOL Bit
(b) MSB1ST
(c) DOSTAT
(d) TCPOL
(e) RCPOL
(f) TDINV
(g) RDINV
Figure 3.17.5 Timing Diagram of Data Receptions Controlled by the TCPOL Bit
SPCLK pin (TCPOL = 0)
SPCLK pin (TCPOL = 1)
SPCLK pin (RCPOL = 0)
SPCLK pin (RCPOL = 1)
SPDI pin
LSB first. Data transmission or reception must not be performed while changing the
state of this bit.
performed (i.e., after completing data transmission or during data reception). Data
transmission or reception must not be performed while changing the state of this bit.
transmission.
time, RCPOL should also be cleared to 0.
reception.
TCPOL should also be cleared to 0.
or not. Data transmission or reception must not be performed while changing the state
of this bit.
not. Data transmission or reception must not be performed while changing the state of
this bit.
This bit specifies whether to transmit/receive byte with the MSB first or with the
This bit specifies the status of the SPDO pin of when data transmission is not
This bit specifies the polarity of the active edge of the synchronization clock for data
The XEN bit should be cleared to 0 for changing the state of this bit. At the same
This bit specifies the polarity of the active edge of the synchronization clock for data
The SPIMD<XEN> bit should be cleared to 0 for changing the state of this bit.
This bit specifies whether to logically invert the data transmitted from the SPDO pin
This bit specifies whether to logically invert the data received from the SPDI pin or
SPDO pin
92CF26A-484
LSB
Bit 0
LSB
Bit 0
Bit 1
Bit 1
Bit 2
Bit 2 Bit 3 Bit 4
Bit 3 Bit 4
MSB
Bit 7
Bit 7
MSB
TMP92CF26A
2007-11-21