TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 93

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

HDMACAn
bit Symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Note: Read-modify-write instructions can be used on all these registers.
(3) HDMACAn (DMA Transfer Count A Setting Register)
performed by one DMA request. HDMACAn contains 16 bits and can specify up to
65536 transfers (0001H = one transfer, FFFFH = 65535 transfers, 0000H = 65536
transfers). Even when the transfer count A is updated by DMA execution, HDMACAn
is not updated.
The HDMACAn register is used to set the number of times a DMA transfer is to be
HDMACA0 to HDMACA5 have the same configuration.
DnCA15
DnCA7
Transfer count A
15
7
0
0
(0909H)
(0919H)
(0929H)
(0939H)
(0949H)
(0959H)
[15:8]
DnCA14
DnCA6
14
6
0
0
Figure3.6.4 HDMACAn Register
DnCA13
DnCA5
HDMACAn Register
13
5
0
0
Transfer count A
92CF26A-92
Transfer count A [15:8] for DMAn
Transfer count A [7:0] for DMAn
HDMACA0
HDMACA1
HDMACA2
HDMACA3
HDMACA4
HDMACA5
(0908H)
(0918H)
(0928H)
(0938H)
(0948H)
(0958H)
[7:0]
DnCA12
DnCA4
12
4
0
0
R/W
R/W
DnCA11
DnCA3
11
3
0
0
DnCA10
DnCA2
10
2
0
0
DnCA1
DnCA9
1
9
0
0
TMP92CF26A
DnCA0
DnCA8
2007-11-21
0
8
0
0