TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 194

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

(6) Timing adjustment function for control signals
TAC:The delay from A23-A0 to CSn, CSZx, CSXx, R/W.
TCWS:The delay from CSn to WRxx,SRWR,SRxxB.
TCWH:The delay from WRxx,SRWR,SRxxB to CSn.
TCRH:The delay from RD,SRxxB to CSn.
CSTMGCR<TxxSEL1:TxxSEL0>, WRTMGCR<TxxSEL1:TxxSEL0>
CSTMGCR<TAC1:TAC0>
WRTMGCR<TCWS/H1:TCWS/H0>
RDTMGCR0/1<BnTCRH1:BnTCRH0>
time requirements of memories.
signals (generated in a write cycle), their timing can be adjusted for only one CS space. As
for the
individually for each of all CS spaces. As for the CS and EX spaces for which the timing
adjustment is not performed, the buses connected to them operate with basic bus timing.
(Refer to (7).)
CSn
This function allows for the timing adjustment of the rising and falling edges of the
As for the
This function can not be used while the BnCSH<BnREC> bit is enabled.
The control signals of SDRAM can be adjusted by setting up the SDRAM controller.
,
CSZx
RD
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
,
CSXx
and
CSn
, R/
SRxxB
,
CSZx
W
,
signals (generated in a read cycle), their timing can be adjusted
,
RD
Change the bus timing for CS0 space
Change the bus timing for CS1 space
Change the bus timing for CS2 space
Change the bus timing for CS3 space
CSXx
TCWS/H = 0.5 × f
,
WRxx
TCRH = 0 × f
TAC = 0 × f
and R/
92CF26A-193
TCWS/H = 1.5 × f
TCWS/H = 2.5 × f
TCWS/H = 3.5 × f
TCRH = 1 × f
TCRH = 2 × f
TCRH = 3 × f
TAC = 1 × f
TAC = 2 × f
,
(Reserved)
SRWR
W
SYS
SYS
signals, and also for the
and
SYS
(Default)
SYS
SYS
(Default)
SYS
SYS
SYS
(Default)
SYS
SYS
SYS
SRxxB
signals based on the setup and hold
WRxx
,
SRWR
TMP92CF26A
2007-11-21
and
SRxxB