TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 181

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

3.8
3.8.1
Memory Controller (MEMC)
programmable address spaces:
(1) Four programmable address spaces
(2) Memory specification
(3) Data bus width specification
(4) Wait control
The TMP92CF26A has a memory controller with the following features to control four
Functional Overview
spaces (CS0 to CS3 spaces).
selected address spaces.
wait state bits of the control register and the
of a read cycle and that of a write cycle can be specified individually. The number of wait
states can be selected from the following 15 options:
* SRAM or ROM: All CS spaces (CS0 to CS3) can be assigned.
* SDRAM: Either the CS1 or CS2 space can be assigned.
* Page-ROM: Only the CS2 space can be assigned.
* NAND-Flash: It is not required to setup the CS lines. However, when using
The MEMC can specify a start address and a block size for each of the four memory
The MEMC can specify the type of memory, SRAM, ROM, SDRAM to associate with the
The data bus width is selectable from 8 and 16 bits for the respective chip select spaces.
The number of wait states to be inserted into an external bus cycle is determined by the
0 to 10 wait states, 12 wait states,
16 wait states, 20 wait states
4+N wait states (controlled by the WAIT pin)
NAND-Flash, set the BROMCR<CSDIS> bit to 1 to assign an
external area to avoid data conflicts with CS spaces.
92CF26A-180
WAIT
input pin. The number of wait states
TMP92CF26A
2007-11-21