TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 377

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

USBINTFR1
(07F0H)
Prohibit to
read-
modify-
write
Note: The above interrupts can release Halt state from IDLE2 and IDLE1 mode. (STOP mode cannot be released)
*Those 6 interrupts of all 24 INTUSB sources can release Halt state from IDLE1 mode. Therefore, a low power dissipation
system can be built. However, the method of use is limited as below.
Shift to IDLE1 mode :
Release from IDLE1 mode :
bit Symbol
Read/Write
Reset State
Function
Execute Halt instruction when the INT_SUS or INT_CLKSTOP flag is “1” ( SUSPEND state )
Release Halt state by INT_RESUME or INT_CLKON request (request of release SUSPEND )
Release Halt state by INT_URST_STR or INT_URST_request (request of RESET )
•
•
•
•
•
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INT_URST_STR
When read 0: Not generate interrupt
INT_URST_STR (Bit7)
INT_URST_END (Bit6)
INT_SUS (Bit5)
INT_RESUME (Bit4)
INT_CLKSTOP (Bit3)
INT_CLKON (Bit2)
R/W
7
0
This is the flag register for INT_URST_STR (“USB reset” start - interrupt).
This is set to “1” when the UDC started to receive a “USB reset” signal from a
USB-host.
An application program has to initialize the whole UDC with this interrupt.
This is the flag register for INT_URST_END (“USB reset” end - interrupt).
This is set to “1” when the UDC receives a “USB reset end” signal from a
USB-host.
This is the flag register for INT_SUS (suspend - interrupt).
This is set to “1” when the USB changes to “suspend status”.
This is the flag register for INT_RESUME (resume - interrupt).
This is set to “1” when the USB changes to “resume status”.
This is the flag register for INT_CLKSTOP (enables stopping of the clock supply
- interrupt).
This is set to “1” when the USB enables a stopping of the clock supply after
changing to “suspend status”.
This is the flag register for INT_CLKON (enabled starting clock supply -
interrupt).
This is set to “1” when the USB enables a starting of the clock supply after
changing to “resume status”.
1: Generate interrupt
INT_URST_END
R/W
6
0
92CF26A-376
INT_SUS
R/W
5
0
When write
INT_RESUME
R/W
4
0
1: −
0: Clear flag
INT_CLKSTOP
R/W
3
0
INT_CLKON
R/W
2
0
TMP92CF26A
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2007-11-21
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