TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 440

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

INT_SETUP
INT_ ENDPOINT0
INT_STATUS
REQUEST FLAG
DATASET register
BRD
BWR
SETUP DATA0 ACK
Figure 3.16.12 The Control Flow in UDC (Control Write Transfer Type not Dataphase)
bmRequestType register
bRequest register
wValue register
wINdex register
wLength register
These change condition is
Figure 3.16.12.
1.
2.
Stage change condition of control write (no data stage) transfer type
• Start setup stage in the UDC.
• Receive data in request normally and judge. And assert INT_SETUP
• Change data stage in the UDC.
• CPU receives a request from the request register every INT_SETUP
• Judge request and access Setup Received register to inform the UDC that
• The CPU processes receiving data by device request.
• When the CPU finishes transaction, it writes “0” to EP0 bit of EOP register.
• Change status stage in the UDC.
• Return data packet of 0 data to IN token, and change state to IDLE in the
• Assert INT_STATUS interrupt externally when ACK for 0 data packet is
Receive SETUP token from host
Receive IN token from host
interrupt externally.
interrupt.
INT_SETUP interrupt has been recognized.
UDC.
received.
Setup Received register
IN
NAK
92CF26A-439
IN
DATA1
EOP register
ACK
TMP92CF26A
2007-11-21