TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 546

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

LCDHWB8
(0299H)
LCDLDW
(0295H)
LCP0
LD23-LD0
LLOAD
LLOAD
bit Symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
LCDLDDLY<PDT> = 0
LCDLDDLY<PDT> = 1
set in a range of 0 to 1024 pulses of the LCP0 clock.
shown below.
The enable width of the LLOAD signal is specified using LCDLDW<LDW9:0>. It can be
The actual enable width is determined depending on the LCDLDDLY<PDT> setting, as
Enable width = <LDW9:0> + 1
Enable width = <LDW9:0>
When LCDCTL0<LCP0OC>=1, the enable width of the LLOAD signal is shown below.
LGOE2 width (bits 9-8) LGOE1 width (bits 9-8)
LDW7
O2W9
7
7
0
0
LDW6
O2W8
6
0
6
0
Signal width Bit8,9 Register
LLOAD width Register
92CF26A-545
O1W9
LDW5
(when <PDT> = 0)
5
5
0
0
LLOAD width (bits 7-0)
LDW4
O1W8
(when <PDT> = 1, <LDW9:0>=0 is prohibited)
4
4
0
0
W
W
width (bit 8)
LGOE0
LDW3
O0W8
3
3
0
0
LLOAD width (bits 9-8)
LDW9
LDW2
2
2
0
0
LDW1
LDW8
1
1
0
0
TMP92CF26A
2007-11-21
width (bit 8)
LHSYNC
HSW8
LDW0
0
0
0
0