TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 566
TMP92CF26AXBG
Manufacturer Part Number
TMP92CF26AXBG
Description
Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
Manufacturer
Toshiba
Datasheet
1.TMP92CF26AXBG.pdf
(767 pages)
Specifications of TMP92CF26AXBG
Processor Series
TLCS-900
Core
900/H
Data Bus Width
16 bit
Program Memory Type
ROM
Program Memory Size
8 KB
Data Ram Size
144 KB
Interface Type
I2C, I2S, UART, USB
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
136
Number Of Timers
10
Maximum Operating Temperature
+ 50 C
Mounting Style
SMD/SMT
Package / Case
FBGA-228
Development Tools By Supplier
BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
Minimum Operating Temperature
0 C
On-chip Adc
10 bit, 6 Channel
Lead Free Status / Rohs Status
Details
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
TMP92CF26AXBG
Manufacturer:
TOSHIBA
Quantity:
4 000
Part Number:
TMP92CF26AXBG
Manufacturer:
TOSHIBA/东芝
Quantity:
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LCDMODE1<INTMODE>=0
LCDMODE1<INTMODE>=1
LVSYNC
LHSYNC
LLOAD
D15-0(VRAM Read)
Interrupt request
Interrupt request
LCDMODE1
(0281H)
3.19.4
Note: The interrupt request generates when reading the data from VRAM at once. Since reading from VRAM is
Note: The LCDMODE1<INTMODE> setting must not be changed while the LCDC is operating. Be sure to set
bit Symbol
Read/Write
Reset State
Function
synchronous with the LLOAD signal that is output immediately after the LVSYNC signal.
each VRAM read before the LLOAD generates (once in each LLOAD period).
VRAM read before the first LLOAD generates (once in each LVSYNC period).
Interrupt Function
The LCDC has two types of interrupts.
One is generated synchronous with the LLOAD signal and the other is generated
LCDMODE1<INTMODE> is used to switch between these two types of interrupts.
When LCDMODE1<INTMODE>=0, an interrupt request is generated at the start of
When LCDMODE1<INTMODE>=1, an interrupt request is generated at the start of
executed by DMA with bus request to the CPU, DMA operation is given priority. Thus CPU accepts interrupt
immediately after reading the data from VRAM.
LCDCTL0<START> to “0” to stop the LCDC operation before changing the interrupt setting.
Data rotation function
(Supported for 64K-color: 16bps
only)
000: Normal
001: Horizontal flip 101: Reserved
010: Vertical flip
011: Horizontal & vertical flip
111: Reserved
LDC2
7
0
LDC1
6
0
100: 90-degree
110: Reserved
LCDMODE1 Register
92CF26A-565
LDC0
5
0
R/W
LD bus
inversion
0: Normal
1: Invert
LDINV
4
0
Auto bus
inversion
0: Disable
1: Enable
(Valid only
for TFT)
AUTOINV
3
0
Interrupt
selection
0:LLOAD
1:LVSYNC
INTMODE
2
0
LFR edge
0: LHSYNC
1:LHSYNCR
FREDGE
Front
Edge
EAR Edge
1
0
TMP92CF26A
W
LD bus
Trance
Speed
0: normal
1: 1/3
2007-11-21
SCPW2
0
0
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