TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 6

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

(LD23, EO_TRGOUT) PU7
(TA1OUT, MLDALM) PM1
(AN4 to AN5)PG4 to PG5
(
(AN0 to AN1)PG0 to PG1
(LGOE2 to 0) PK7 to 5
(AN3, MY, ADTRG )PG3
(
(LD22 to 16) PU6 to 0
SDCAS
(TA7OUT, INT5) PP3
(CLKOUT, LDIV) PX4
(
SDRAS
(TB0IN0, INT6) PP4
(TB1IN0, INT7) PP5
(LD15 to 8) PT7 to 0
SDWE
(TA0IN, INT1) PC1
(TA2IN, INT3) PC3
(LD7 to 0) PL7 to 0
(CTS0, SCLK0) P92
(SDLUDQM) PJ4
(SDLLDQM) PJ3
(TB0OUT0) PP6
(TB1OUT0) PP7
(I2S0CKO) PF0
(I2S1CKO) PF3
(TA3OUT) PP1
(LHSYNC) PK4
(TA5OUT) PP2
(I2S0WS) PF2
(I2S1WS) PF5
(LVSYNC) PK3
VREFH, VREFL
(I2S0DO) PF1
(I2S1DO) PF4
,
(SDCLK) PF7
(PX, INT4) P96
(AN2, MX)PG2
(SPCLK) PR3
(SDCKE) PJ7
(LLOAD) PK1
,
,
(SPDO) PR1
(
(X1USB) PX5
SRLUB
SRLLB
SRWR
AVCC, AVSS
(RXD0) P91
(TXD0) P90
(SPDI) PR0
(LCP0) PK0
SPCS
(SDA) PV6
(LFR) PK2
(SCL) PV7
(PY) P97
) PJ0
) PR2
) PJ1
) PJ2
PX7
D -
D+
16BIT TIMER
16BIT TIMER
SERIAL I/O
SBI (I
Touch Screen
8BIT TIMER
8BIT TIMER
8BIT TIMER
8BIT TIMER
8BIT TIMER
8BIT TIMER
8BIT TIMER
8BIT TIMER
10-bit 6ch
Converter
Controller
Controller
Controller
Controller
SDRAM
(TMRA0)
(TMRA1)
(TMRA2)
(TMRA3)
(TMRA4)
(TMRA5)
(TMRA6)
(TMRA7)
(TMRB0)
(TMRB1)
(I
(I
SIO0
LCD
(TSI)
USB
SPI
AD
I
2
I
2
I/F
2
2
S0)
S1)
2
S
S
Cbus)
Figure 1.1 Block Diagram of TMP92CF26A
XWA
XBC
XDE
XHL
XIX
XIY
XIZ
XSP
WATCH-DOG TIMER
BOOT ROM 8KB
144KB RAM
900/H1 CPU
SR
92CF26A-5
32bit
P C
DMAC
MMU
MAC
W
B
D
H
SP
IX
IY
IZ
C
A
E
F
L
KEY-BOARD
ALARM-OUT
NAND-FLASH
Clock gear
Controller
MELODY/
Interrupt
PORTV
H-OSC
PORT1
PORT4
PORT5
PORT6
PORT7
PORT8
L-OSC
I/F (2ch)
PMC
DSU
RTC
PLL
I/F
TMP92CF26A
DVCC1C [1]
DVSS1C [1]
DVCC3A [12]
DVCC3B [1]
DVCC1A [5]
DVCC1B [1]
DVSSCOM
D0 to D7
P10 to P17 (D8 to D15)
PV3
PV4
PV0 (SCLK0)
PV1
PV2
PW7 to PW0
RESET
PZ0 (EI_PODDATA)
PZ1 (EI_SYNCLK)
PZ2 (EI_PODREQ)
PZ3 (EI_REFCLK)
PZ4 (EI_TRGIN)
PZ5 (EI_COMRESET)
PZ6 (EO_MCUDATA)
PZ7 (EO_MCUREQ)
PM7 (PWE)
PC0 (INT0)
PC2 (INT2)
P40 to P47 (A0 to A7)
P50 to P57 (A8 to A15)
P60 to P67 (A16 to A23)
P70 ( RD )
P73 (EA24)
P74 (EA25)
P75 (R/ W , NDR/ B )
P76 ( WAIT )
P80 (
P81 (
P82 (
P83 (
P84 ( CSZB )
P85 ( CSZC )
P71 ( WRLL , NDRE )
P72 ( WRLU , NDWE )
P86 ( CSZD ,
P87 ( CSXB ,
PJ5 (NDALE)
PJ6 (NDCLE)
PA0 to PA7 (KI0 to KI7)
PN0 to PN7 (KO0 to KO7)
PC7 (KO8)
PM2 ( ALARM , MLDALM )
2007-11-21
DBGE
AM [1:0]
PC4 (EA26)
PC5 (EA27)
PC6 (EA28)
X1
X2
XT1
XT2
CS )
CS , SDCS )
CS , CSZA , SDCS )
CS , CSXA )
1
0
2
3
ND
ND
1
0
CE
CE
)
)