TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 314
![no-image](/images/manufacturer_photos/0/6/668/toshiba_sml.jpg)
TMP92CF26AXBG
Manufacturer Part Number
TMP92CF26AXBG
Description
Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
Manufacturer
Toshiba
Datasheet
1.TMP92CF26AXBG.pdf
(767 pages)
Specifications of TMP92CF26AXBG
Processor Series
TLCS-900
Core
900/H
Data Bus Width
16 bit
Program Memory Type
ROM
Program Memory Size
8 KB
Data Ram Size
144 KB
Interface Type
I2C, I2S, UART, USB
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
136
Number Of Timers
10
Maximum Operating Temperature
+ 50 C
Mounting Style
SMD/SMT
Package / Case
FBGA-228
Development Tools By Supplier
BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
Minimum Operating Temperature
0 C
On-chip Adc
10 bit, 6 Channel
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TMP92CF26AXBG
Manufacturer:
TOSHIBA
Quantity:
4 000
Part Number:
TMP92CF26AXBG
Manufacturer:
TOSHIBA/东芝
Quantity:
20 000
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Match with TB0RG0H/L
Match with TB0RG1H/L
(Value to be compared)
Note: The values that can be set in TBxRGx range from 0001h to 0000h (equivalent to 10000h). If the maximum value
(3) 16-bit programmable pulse generation (PPG) output mode
Register buffer 10
Match with TB0RG0
Match with TB0RG1
(INTTB00 interrupt)
(INTTB01 interrupt)
Figure 3.13.9 Programmable Pulse Generation (PPG) Output Waveforms
000h is set, the match-detect signal goes active when the up-counter overflows.
pulse may be either low active or high active.
by the match of the up counter UC10 with timer register TB0RG0H/L or TB0RG1H/L
and is output to TB0OUT0. In this mode the following conditions must be satisfied.
buffer 10 will be shifted into TB0RG0H/L at match with TB0RG1H/L. This feature
facilitates the handling of low-duty waves.
Square wave pulses can be generated at any frequency and duty ratio. The output
The PPG mode is obtained by inversion of the timer flip-flop TB0FF0 that is enabled
When the TB0RG0H/L double buffer is enabled in this mode, the value of register
TB0RG0H/L
TB0OUT0 pin
(Value set in TB0RG0) < (Value set in TB0RG1)
Figure 3.13.10 Operation of double buffer
Up conter = Q
92CF26A-313
Q
1
1
Q
2
Shift into TB0RG1H/L
Up counter = Q
Q
2
Write into TB0RG0H/L
2
TMP92CF26A
Q
3
2007-11-21
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