TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 224

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

3.10 SDRAM Controller (SDRAMC)
can be used as data memory, program memory, or display memory.
(1) Supported SDRAM
(2) Supported initialization sequence commands
(3) Access mode
(4) Access cycles
(5) Auto generation of refresh cycles
The TMP92CF26A incorporates an SDRAM controller (SDRAMC) for accessing SDRAM that
The SDRAMC has the following features:
•
•
•
CAS latency (clock)
Note: The SDRAM address area is determined by the CS1 or CS2 setting of the memory controller. However, the
Data rate type
Memory capacity
Number of banks
Data bus width
Read burst length
Write mode
Precharge All command
Eight Auto Refresh commands
Mode Register Set command
CPU access cycles
HDMA access cycles
LCDC access cycles
Addressing mode
Auto Refresh is performed while the SDRAM is not being accessed.
The Auto Refresh interval is programmable.
The Self Refresh function is also supported.
Burst length
Write mode
Read cycle
Write cycle
Data size
Read cycle
Write cycle
Data size
Read cycle
Data size
number of bus cycle states is controlled by the SDRAMC.
: 1 word, 4-3-3-3 states (minimum)
: Single, 3-2-2-2 states (minimum)
: 1 byte / 1 word / 1 long-word
: 1 word, 4-3-3-3 states / full page, 4-1-1-1 states (minimum)
: Single, 3-2-2-2 states (minimum) / burst, 2-1-1-1 states (minimum)
: 1 byte / 1 word / 1 long-word
: Full page, 4-1-1-1 states (minimum)
: 1 word
: SDR (single data rate) type only
: 16 / 64 / 128 / 256 / 512 Mbits
: 2 banks / 4 banks
: 16 bits
: 1 word / full page
: Single mode / Burst mode
CPU Cycle
Sequential
1 word
Single
2
92CF26A-223
1 word or full page selectable
Single or burst selectable
HDMA Cycle
Sequential
2
LCDC Cycle
Sequential
Full page
2
TMP92CF26A
2007-11-21