TMP92CF26AXBG Toshiba, TMP92CF26AXBG Datasheet - Page 358

• Manufacturer Part Number: TMP92CF26AXBG
• Description: Microcontrollers (MCU) TLCS-900/H1 ROMLESS 144KB RAM
• Manufacturer: Toshiba

Specifications of TMP92CF26AXBG

• Processor Series: TLCS-900
• Core: 900/H
• Data Bus Width: 16 bit
• Program Memory Type: ROM
• Program Memory Size: 8 KB
• Data Ram Size: 144 KB
• Interface Type: I2C, I2S, UART, USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 136
• Number Of Timers: 10
• Maximum Operating Temperature: + 50 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-228
• Development Tools By Supplier: BM1040R0A, BM1055R0B, SW96CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 6 Channel
• Lead Free Status / Rohs Status: Details

SCL pin
Internal SDA output
(Master A)
Internal SDA output
(Master B)
SDA pin
(8)
(9)
(10)
is cleared to “0”. During the time that the SBICR2<PIN> is “0”, the SCL line is pulled
down to the Low level.
The <PIN> is cleared to “0” when a 1-word of data is transmitted or received. Either
writing/reading data to/from SBIDBR sets the <PIN> to “1”.
The time from the <PIN> being set to “1” until the SCL line is released takes tLOW.
In the address recognition mode (<ALS> = “0”), <PIN> is cleared to “0” when the
received slave address is the same as the value set at the I2CAR or when a GENERAL
CALL is received (all 8-bit data are “0” after a start condition). Although
SBICR2<PIN> can be set to “1” by the program, the <PIN> is not clear it to “0” when it
is written “0”.
SBICR2< SBIM1:0> to “10” when the device is to be used in I2C Bus Mode after
confirming pin condition of serial bus interface to “H”.
Switch a mode to port after confirming a bus is free.
Mode, a bus arbitration procedure has been implemented in order to guarantee the
integrity of transferred data.
and SDA pin, but arbitration lost is generated.
Data on the SDA line is used for I2C bus arbitration.
The following shows an example of a bus arbitration procedure when two master
devices exist simultaneously on the bus. Master A and Master B output the same data
until point “a”. After Master A outputs “L” and Master B, “H”, the SDA line of the bus
is wire-AND and the SDA line is pulled down to the Low-level by Master A. When the
SCL line of the bus is pulled up at point b, the slave device reads the data on the SDA
line, that is, data in Master A. A data transmitted from Master B becomes invalid. The
state in Master B is called “ARBITRATION LOST”. Master B device which loses
arbitration releases the internal SDA output in order not to affect data transmitted
from other masters with arbitration. When more than one master sends the same data
at the first word, arbitration occurs continuously after the second word.
Interrupt service requests and interrupt cancellation
Serial bus interface operation mode selection
Arbitration lost detection monitor
When a serial bus interface interrupt request (INTSBI) occurs, the SBICR2 <PIN>
SBICR2<SBIM1:0> is used to specify the serial bus interface operation mode. Set
Since more than one master device can exist simultaneously on the bus in I2C Bus
In case set start condition bit with bus is busy, start condition is not output on SCL
Figure 3.15.12 Arbitration lost
92CF26A-357
a
b
Internal SDA output becomes 1 after arbitration has been lost.
TMP92CF26A
2007-11-21