HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 102

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

HFC-E1
The FIFO number is always the same as the HFC-channel number whereas the PCM time
slot number can be chosen independently from the HFC-channel number.
Due to the fixed correspondence between FIFO number and HFC-channel, a pair of transmit
and receive FIFOs is allocated even if a bidirectional data connection between the PCM
interface and the E1 interface is established. Please note that in this case the FIFO must be
enabled to enable the data transmission.
A direct coupling of two PCM time slots uses a PCM switching buffer. This connection
requires a HFC-channel number (resp. the same FIFO number). An arbitrary HFC-channel
number can be chosen. If there are less than 31 transmit and receive FIFOs it is usefull
to chose a HFC-channel number that is greater than the maximum FIFO number generally.
This saves FIFO resources where no data is stored in a FIFO.
Subchannel processing
In most applications the subchannel processor is not used in Simple Mode. However, if the
data stream of a FIFO does not require full 8 kByte/s data rate, the subchannel processor
might be used. Unused bits can be masked out with an arbitrary mask byte.
In transparent mode only the non-masked bits of a byte are transmitted. Masked bits are taken
from the register A_CH_MSK. So the effective FIFO data rate always remains 8 kByte/s
whereas the usable data rate depends on the number of non-masked bits.
In HDLC mode the data rate of the FIFO is reduced according to how many bits are not
masked out.
Please see Section 3.5 on page 113 for details concerning the subchannel processor.
Example for SM
Figure 3.5 shows an example with three bidirectional connections (FIFO-to-E1, FIFO-to-
PCM and PCM-to-E1). The FIFO box on the left side contains number and direction of
the used FIFOs. The E1 and PCM boxes on the right side contain the E1 time slots and
PCM time slot numbers and directions which are used in this example. Black lines illustrate
data paths, whereas dotted lines symbolize blocked resources. These are not used for data
transmission, but they are necessary to enable the settings.
The following settings demonstrate the required register values to establish the connection.
All involved FIFOs have to be enabled with V_HDLC_TRP
register A_CON_HDLC[FIFO]. The non-specified bitmap values depend on the desired
FIFO configuration.
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G
All settings in Figure 3.5 are configured in bidirectional data paths due
to typical applications of the HFC-E1. However, transmit and receive
directions are independent from each other and could occur one at a time
as well.
Please note !
Data Sheet
Data flow
·
V_TRP_IRQ
March 2003 (rev. A)
Cologne
Chip
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in the