HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 243

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

March 2003 (rev. A)
HFC-E1
R_IRQ_FIFO_BL0
FIFO interrupt register for FIFO block 0
In HDLC mode the end of frame is signaled, while in transparent mode the fre-
quency of interrupts is set in the bitmap V_TRP_IRQ of the register A_CON_HDLC.
The bit value ’1’ indicates that the corresponding FIFO generated an interrupt. If
a bit is ’0’, no interrupt occured in the corresponding FIFO.
Reading this register clears all set bits and the corresponding bit of the register
R_IRQ_OVIEW.
0
1
2
3
4
5
6
7
Bits
0
0
0
0
0
0
0
0
Value
Reset
Name
V_IRQ_FIFO0_TX
V_IRQ_FIFO0_RX
V_IRQ_FIFO1_TX
V_IRQ_FIFO1_RX
V_IRQ_FIFO2_TX
V_IRQ_FIFO2_RX
V_IRQ_FIFO3_TX
V_IRQ_FIFO3_RX
Clock, reset, interrupt, timer and watchdog
(read only)
Data Sheet
Description
Interrupt occured in transmit FIFO 0
Interrupt occured in receive FIFO 0
Interrupt occured in transmit FIFO 1
Interrupt occured in receive FIFO 1
Interrupt occured in transmit FIFO 2
Interrupt occured in receive FIFO 2
Interrupt occured in transmit FIFO 3
Interrupt occured in receive FIFO 3
Cologne
Chip
243 of 272
0xC8