HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 74

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

HFC-E1
8 bit processors write data like shown in Figure 2.14. Timing values are listed in Table 2.24.
/BE3 . . . /BE1 must always be ’1’. /BE0 controls the data bus D7 . . . D0 and can be fixed
to ’0’.
Data is written with of (/WR
a data setup time
Address and /BE0 (if not fixed to low) require a setup time
ALE. The hold time of these lines is
address, multiple register address write is not required.
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/WR+/CS
AD[31:8]
/BE[3:1]
A[7:0]
/BE0
ALE
/RD
Figure 2.14: Write access from 8 bit processors in mode 4 (Intel, multiplexed)
t
address
ALE
Ø
t
AS
address
Ï Ë
t
AH
and a data hold time
t
ALEH
Universal external bus interface
·
/CS) in mode 4 (Intel, multiplexed). The HFC-E1 requires
Ø
À
byte write access
Data Sheet
. If two consecutive write accesses are on the same
t
t
DWRS
WR
permanently high
permanently high
permanently low
data
Ø
Ï À
.
t
DWRH
t
IDLE
Ø
Ë
which starts with the
byte write access
t
t
WR
DWRS
March 2003 (rev. A)
data
Cologne
Chip
t
DWRH
of