HFC-S2M Cologne Chip AG, HFC-S2M Datasheet - Page 269

• Manufacturer Part Number: HFC-S2M
• Description: Isdn HDLC Fifo Controller With Primary Rate Interface
• Manufacturer: Cologne Chip AG

List of register and bitmap abbreviations
This list shows all abbreviations which are used to define the register and bitmap names.
Appended digits are not shown here except they have a particular meaning.
A
ADDR
ADDR0
ADDR1
ADDR2
ADJ
AIS
ALT
ATT
ATX
AUTO
BERT
BIT
BL
BRG
BUSY
C4
CFG
CH
CHANNEL HFC-channel
CHG
CHIP
CLK
CMI
CNT
CNTH
CNTL
CODE
CON
March 2003 (rev. A)
A bit
address
address (byte 0)
address (byte 1)
address (byte 2)
adjust
alarm indication
signal
alternate
attenuation
analog transmitter
automatic
bit error rate test
bit
block
bridge
busy
C4IO clock
configuration
HFC-channel
changed
chip
clock
code mark
inversion
counter
counter, high byte
counter, low byte
code
connection settings
COND
CONF
CRC
CS
CSM
CTRL
DATA
DEC
DEL
DIR
DR
DTMF
E
E1
E1RES
E2
ECH
ECL
EN
END
EOMF
EPR
ERR
EV
EXCHG
EXT
Data Sheet
condition
conference
cyclic redundancy
check
chip select
channel select
mode
control
data
decoder
deletion
direction
data rate
dual tone multiple
frequency
CRC error
indication bits
error counter, high
byte
error counter, low
byte
enable
end
end of multiframe
error
exchange
external
E1 bit
E1 interface reset
E2 bit
EEPROM
event
F
F0
F1
F12
F2
FAS
FBAUD
FG
FIFO
FIRST
FLOW
FOSLIP
FOSTA
FR
FSM
GLOB
GPI
GPIO
HARM
HCLK
HDLC
HFCRES
F-counter
frame
syncronization
signal
F1-counter
F1- and F2-counter
F2-counter
frame alignment
signal
full bauded
F/G state
FIFO
first
flow
force frequency slip
warning
force state
frame
FIFO sequence
mode
global
general purpose
input
general purpose
input/output
harmonic
half clock
(frequency)
high-level data link
control
HFC reset
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